Designer’s Guide Community

purplewolf

Senior Member

Offline

Posts: 103

sizing differential pair transitors
Aug 04^th, 2011, 4:31am

I simulated a differential pair with ideal tail current source from 500uA-3mA The width of diff pair transistory were kept contact to 12u in 180 nm CMOS. I found out that the circuit gives good performance at 1.4mA. The next task would be replace the ideal current source with current mirror. But how do i size the diff pair transistors. Is 12u width enough for 1.4 mA tail current...The Spectre does not give me anysort of error. whats the tradeoffs and am i missing something.??..

Back to top

IP Logged

Lex Senior Member Offline Posts: 201 Eindhoven, Holland	Re: sizing differential pair transitors Reply #1 - Aug 4^th, 2011, 5:06am The current density doesn't looks very extreme, so I think you'll be fine. Check your PDK doc's for confirmation. Needless to say, watch your layout to avoid limitations by Ohmic drops, or even in worst case, burning metal tracks. ><
Back to top	IP Logged

purplewolf

Senior Member

Offline

Posts: 103

Re: sizing differential pair transitors
Reply #2 - Aug 4^th, 2011, 5:34am

I want to understand the relation between tail current transsitor W/L and the diff pair transistor W/L.. Since, when the diff pair transistor is fully on, Itail will flow through it. Why not make it equal to Itail device?? But it will have huge parasitic capacitance associated with it!! Whats the criteria of sizing diff pair device so that its dimension is optimum and robust and will work in all environments..

Back to top

IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: sizing differential pair transitors Reply #3 - Aug 4^th, 2011, 5:53am simple questions: Where are the transistors functioning on a set of bias curves? What is the optimal matching geometry for the process? Have you done the differential pair with a set of M=2 transistors, so that you can common centroid the differential pair in the layout?
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

purplewolf

Senior Member

Offline

Posts: 103

Re: sizing differential pair transitors
Reply #4 - Aug 4^th, 2011, 6:10am

loose-electron wrote on Aug 4^th, 2011, 5:53am:

simple questions:

Where are the transistors functioning on a set of bias curves?
The diff pair is a part of charge pump which will get input from PFD. How do i get its functioning from set of bias curves as you are mentioning.
What is the optimal matching geometry for the process?
I dont know about this
Have you done the differential pair with a set of M=2 transistors, so that you can common centroid the differential pair in the layout?

I have multiplier factor of 2. But what about its width and length adjustment. What is i choose other multiplier factor

Back to top

IP Logged

purplewolf

Senior Member

Offline

Posts: 103

Re: sizing differential pair transitors
Reply #5 - Aug 4^th, 2011, 6:11am

Repost.
simple questions:

Where are the transistors functioning on a set of bias curves?
ANSWER:The diff pair is a part of charge pump which will get input from PFD. How do i get its functioning from set of bias curves as you are mentioning.
What is the optimal matching geometry for the process?
ANSWER:I dont know about this
Have you done the differential pair with a set of M=2 transistors, so that you can common centroid the differential pair in the layout?
ANSWER: I have multiplier factor of 2. But what about its width and length adjustment. What is i choose other multiplier factor

Back to top

IP Logged

loose-electron

Senior Fellow

Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California

Re: sizing differential pair transitors
Reply #6 - Aug 4^th, 2011, 7:49am

That is not a differential pair, as in the input of an op-amp. What you are describing is a set of current steering switches, in an H-bridge configuration.

Different considerations for that. Minimum geometry for devices, at the weakest process corner and the most expected current in the devices. That gets you to the smallest sized device to steer current.

For this application, the reason you are trying to get to the smallest devices is so that you minimize charge injection into the loop filter.

Back to top

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

IP Logged

purplewolf

Senior Member

Offline

Posts: 103

Re: sizing differential pair transitors
Reply #7 - Aug 5^th, 2011, 2:34am

The peak current that passes though the current steering switches is equal to Itail. If the size of tail current device is 100u and the size of steering device is 12u, will there be any physical reliability issues on part of steering device due to its smaller size and more current passing through it?
The physical reliability issues can be adressed through weakest process corner??
Am i thinking in right direction??.

Back to top

IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: sizing differential pair transitors Reply #8 - Aug 6^th, 2011, 11:21am look thru your foundry data for information available on max current vs. device size. Might be with the electromigration stuff, but this is something different.
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged