hello,
what do you mean by SB-pll. Any how if you are asking for normal pll, by increasing Feedback divider all refclk jitter, pfd-cp phase noise will get amplified. So area under the curve will increase, hence more timing jitter. But you have to see how your VCO noise is changing. So for this type questions you should really plot all phase noise with appropriate noise transfer functions and get the area under the curve.

Thanks.