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How to choose transistor sizes in CMOS PA
Sep 08^th, 2011, 11:46pm

HI,
I'm design a 65nm CMOS PA for WiMax with on-chip transformer as the output impedance transformation network. The maximum output power is larger than 30dBm. I'm confusing that how to choose the transistor sizes. As we know, if the output power is very large, transistor sizes must be large too. But how can I know what the accurate sizes are with an fixed maximum output power?

Thank you!

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prakash@191 New Member Offline Posts: 3 India	Re: How to choose transistor sizes in CMOS PA Reply #1 - Oct 19^th, 2011, 12:17pm The length of the transistor should be not changed as far as i know. Because the technology has to to maintained constant. For the less power dissipation you should have more width for a given transistor. Let me know what you mean by accurate sizes.
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watson822 New Member Offline Posts: 3 Taiwan	Re: How to choose transistor sizes in CMOS PA Reply #2 - Oct 26^th, 2011, 3:56am I have this question before. In my opinion, under fixed Vcc and required output power, you can get bias current Ic from load-line principle. Then, choose transistor size based on the current density of metal trace.
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Re: How to choose transistor sizes in CMOS PA
Reply #3 - Oct 26^th, 2011, 4:56am

prakash@191 wrote on Oct 19^th, 2011, 12:17pm:

The length of the transistor should be not changed as far as i know. Because the technology has to to maintained constant.
For the less power dissipation you should have more width for a given transistor.
Let me know what you mean by accurate sizes.

I mean when supply voltage and maximum saturated power is given, how can I choose the transistor width? thx

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Re: How to choose transistor sizes in CMOS PA
Reply #4 - Oct 26^th, 2011, 4:59am

watson822 wrote on Oct 26^th, 2011, 3:56am:

I have this question before. In my opinion, under fixed Vcc and required output power, you can get bias current Ic from load-line principle. Then, choose transistor size based on the current density of metal trace.

would you give some suggestions for the load-line simulation?
how to set the simulation load R? R equals Rload? or the optimum Ropt?

Thank you!

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: How to choose transistor sizes in CMOS PA Reply #5 - Oct 26^th, 2011, 11:49am A load line? That is not a simulation. Please look the subject up in a basic transisotr level design textbook. This is going to be a good way to get a basic operating point for a first pass at the design. To be more helpful, you need to be more specific about what you need.
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Re: How to choose transistor sizes in CMOS PA
Reply #6 - Nov 17^th, 2011, 8:23am

The load line concept is good for PA's! I would look at the transistor saturation voltage. If it should be low for good efficiency (like 150mV), than maybe the transistor Cgs becomes large and speed, gain low. So a compromise it needed - also for best reliability. At the end not all can be really simulated... Huh

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