Ywguo,

First of all, mmsim 07.20.194 is fairly old. Did you try a recent version?
I checked the code of the standard E2L module and it seemed OK, so perhaps a simulator bug?
However, a few additional ideas: What parameters do you use for in your connect rules? Which rules do you use? Is supply present?

B O E

Hi,

A vpulse signal was fed to clock signal of div2, the rise time and fall time are 1ns. The output of E2L_2_inhconn module became x and 1 almost simultaneously at the rise edge of analog voltage pulse. Unfortunately, ncsim regards that 0 -> X as posedge. So the divider by 2 goes up and down. No pulse is visible or there are very very narrow pulse. The width is determined by delta T defined by timescale.

I looked into this E2L_2_inhconn.vams file and E2L_2_inhconn.vams file in IUS installation directory.  The have minor differences, but I think they shall have the same function. However, if I replace myconnectLib with connectLib in IUS installation directory, everything works fine. There are not any X.

The delay to find out X are 0.8ns in both E2L_2_inhconn module. So I think 1ns rise time and fall time is sharp enough to avoid X. But it fails for myConnectlib and works for connectLib in IUS install directory.

The following is part of my E2L_2_inhConn module.
Code:

// INSTANCE PARAMETERS:
  parameter real vsup_min=0.5 from (0:inf); // min supply for normal operation
  parameter real tr=0.2n from (0:1m);		// risetime (for defaults)
  parameter real txdel=4*tr from (0:1m);	   // time midrange til output X
  parameter real ttol_c=tr/4  from (0:1m);	   // time tolerance of crossing
  parameter real tf=tr		 from (0:inf);  // falltime of analog output
  parameter real ttol_t=(tr+tf)/20 from (0:inf);  // time tol of transition
  parameter real tdelay=0	    from [0:inf);  // delay time of analog output
// scaled input/output levels/thresholds (0 maps to Vref, 1 maps to Vsup):
  parameter real vthi=1/1.5 from (0:1);	// frac. for high tresh (def=2/3)
  parameter real vtlo=vthi/2 from (0:vthi);  // frac. for low tresh (def=1/3)
  parameter real vtol=1.0/12 from (0:(vthi-vtlo)/2]; // frac. for vtol
  parameter real vtlox=vtlo+vtol from (vtlo:vthi);  // lo to X state threshold
  parameter real vthix=vthi-vtol from [vtlox:vthi); // hi to X state threshold
// LOCAL VARIABLES:
  reg Dreg;		    // output register
  reg Xin;		     // Tx control registers
  real Vds;		    // supply voltage
  real Vas;		    // input voltage
  real Vdsflag;		// flag if Vds exceeds vsup_min
  real Kin;		    // input relative to supply range
  real txdig;		  // tx in timescale units

//============================================================================
  initial begin
    txdig=txdel/1n;	  // digital delay midlevel to X  (ASSUMES TIMESCALE)
    Dreg=1'b0;		 // initial level
    Xin=0;		     // initially not in X delay region.
  end

// Relative input level (maps input to range of 0=vref, 1=vsup):
//  analog begin
//	Vdsflag = V(\vdd! ,\vss! ) > vsup_min;
//	Kin = V(Ain,\vss! )/max(V(\vdd! ,\vss! ),1m) * transition(Vdsflag,tdelay,tr,tr,ttol_t);
//  end

// Convert analog signal to high/low and X/notX:
  always @(above(Kin-vthi,ttol_c,vtol))
	begin Dreg=1; Xin=0; $display($time, " ns, Dreg=1"); end			 // analog XtoH
  always @(above(vtlo-Kin,ttol_c,vtol))
	begin Dreg=0; Xin=0; $display($time, " ns, Dreg=0"); end			 // analog XtoL
  always @(above(vthix-Kin,ttol_c,vtol)) begin
	$display($time, " ns, Dreg==1'b1, Xin=1");
	if (Dreg==1'b1) Xin=1;			   // analog HtoX
  end
  always @(above(Kin-vtlox,ttol_c,vtol)) begin
	$display($time, " ns, Dreg==1'b0, Xin=1");
	if (Dreg==1'b0) Xin=1;			   // analog LtoX
  end
// Wait for txdel before driving output to X:
  always @(posedge(Xin)) begin			 // input changed to X
    #(txdig)						 // wait for X time delay
    if (Xin==1) begin
	 Dreg=1'bx;			     // goto X if still between
	 $display($time, " ns, Dreg=%b", Dreg);
    end
  end
  assign  Dout=Dreg;				     // assign register to output
  always @(posedge Dreg) begin
     $display($time, " ns, Dreg rises");
  end
  always @(negedge Dreg) begin
     $display($time, " ns, Dreg falls");
  end
// Relative input level (maps input to range of 0=vref, 1=vsup):
 analog begin
   Vds = V(\vdd! ,\vss! );
   Vas = V(Ain,\vss! );
   Vdsflag = Vds > vsup_min;
   Kin = Vas/max(Vds, 1m) * transition(Vdsflag,tdelay,tr,tf,ttol_t);
 end


 

After the rise/fall time of mclk_150k was reduced to 0.1ns, divider-by-2 works. The following is part of simulation log and waveforms.
Code:

Warning from spectre in `cds_globals', during circuit read-in.
    `cds_globals': Parameter `power' redefines parameter of same name defined
	  at higher level.
    `cds_globals': Parameter `Ts' redefines parameter of same name defined at
	  higher level.


Circuit inventory:
		  nodes 4
csmc05mm01_connectLib+E2L_2_inhconn+module+0x10000001 behavioral 2    
		vsource 4    


************************************************
Transient Analysis `tran': time = (0 s -> 15 us)
************************************************
			 0 ns, Dreg==1'b1, Xin=1
			 0 ns, Dreg=0
			 0 ns, Dreg==1'b1, Xin=1
			 0 ns, Dreg=0
			 0ns mclk_150k rises, mclk_150k=0
			 0ns mclk_150k rises, mclk_150k=0
Important parameter values:
    start = 0 s
    outputstart = 0 s
    stop = 15 us
    step = 15 ns
    maxstep = 150 ns
    ic = all
    skipdc = no
    reltol = 100e-06
    abstol(I) = 1 pA
    abstol(V) = 1 uV
    temp = 27 C
    tnom = 27 C
    tempeffects = all
    errpreset = conservative
    method = gear2only
    lteratio = 10
    relref = alllocal
    cmin = 0 F
    gmin = 1 pS

			 0 ns, Dreg==1'b0, Xin=1
			 0 ns, Dreg=1
			 0 ns, Dreg rises
			 0ns mclk_150k rises, mclk_150k=1
		     472 ns, Dreg==1'b0, Xin=1
    tran: time = 472 ns	(3.15 %), step = 139.5 ns     (930 m%)
		     472 ns, Dreg=x
		     472 ns, Dreg rises
		     703 ns, Dreg=1
		     703 ns, Dreg rises
    tran: time = 1.15 us     (7.67 %), step = 150 ns	    (1 %)
    tran: time = 1.889 us    (12.6 %), step = 150 ns	    (1 %)
    tran: time = 2.639 us    (17.6 %), step = 150 ns	    (1 %)
		    2900ns mclk_150k rises, mclk_150k=1
		    3000 ns, Dreg==1'b1, Xin=1
		    3000 ns, Dreg=0
		    3000 ns, Dreg falls
    tran: time = 3.386 us    (22.6 %), step = 150 ns	    (1 %)
    tran: time = 4.136 us    (27.6 %), step = 150 ns	    (1 %)
    tran: time = 4.886 us    (32.6 %), step = 150 ns	    (1 %)
    tran: time = 5.636 us    (37.6 %), step = 150 ns	    (1 %)
		    6000 ns, Dreg==1'b0, Xin=1
		    6000 ns, Dreg=1
		    6000 ns, Dreg rises
		    6000ns mclk_150k rises, mclk_150k=1
    tran: time = 6.386 us    (42.6 %), step = 150 ns	    (1 %)
    tran: time = 7.136 us    (47.6 %), step = 150 ns	    (1 %)
    tran: time = 7.886 us    (52.6 %), step = 150 ns	    (1 %)
    tran: time = 8.636 us    (57.6 %), step = 150 ns	    (1 %)
		    8700ns mclk_150k rises, mclk_150k=1
		    9000 ns, Dreg==1'b1, Xin=1
		    9000 ns, Dreg=0
		    9000 ns, Dreg falls
    tran: time = 9.386 us    (62.6 %), step = 150 ns	    (1 %)
    tran: time = 10.14 us    (67.6 %), step = 150 ns	    (1 %)
    tran: time = 10.89 us    (72.6 %), step = 150 ns	    (1 %)
    tran: time = 11.64 us    (77.6 %), step = 150 ns	    (1 %)
		   12000 ns, Dreg==1'b0, Xin=1
		   12000 ns, Dreg=1
		   12000 ns, Dreg rises
		   12000ns mclk_150k rises, mclk_150k=1
    tran: time = 12.39 us    (82.6 %), step = 150 ns	    (1 %)
    tran: time = 13.14 us    (87.6 %), step = 150 ns	    (1 %)
    tran: time = 13.89 us    (92.6 %), step = 150 ns	    (1 %)
		   14500ns mclk_150k rises, mclk_150k=1
    tran: time = 14.64 us    (97.6 %), step = 150 ns	    (1 %)
Number of accepted tran steps =		 176
Initial condition solution time: CPU = 1 ms, elapsed = 601.053 us.

**** AMSD: Mixed-Signal Activity Statistics ****
Number of A-to-D events:			    16
  Number of A-to-D events in IEs:		 16
Number of D-to-A events:			     0
  Number of D-to-A events in IEs:		  0
Number of VHDL-AMS Breaks:			   0