The following is part of the simulation log and the waveform, where mclk_150k is clock input, and clk_cic is the output of div-by-2.
Code:Warning from spectre in `cds_globals', during circuit read-in.
`cds_globals': Parameter `power' redefines parameter of same name defined
at higher level.
`cds_globals': Parameter `Ts' redefines parameter of same name defined at
higher level.
Circuit inventory:
nodes 4
csmc05mm01_connectLib+E2L_2_inhconn+module+0x10000001 behavioral 2
vsource 4
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Transient Analysis `tran': time = (0 s -> 15 us)
************************************************
0 ns, Dreg==1'b1, Xin=1
0 ns, Dreg=0
0 ns, Dreg==1'b1, Xin=1
0 ns, Dreg=0
0ns mclk_150k rises, mclk_150k=0
0ns mclk_150k rises, mclk_150k=0
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 15 us
step = 15 ns
maxstep = 150 ns
ic = all
skipdc = no
reltol = 100e-06
abstol(I) = 1 pA
abstol(V) = 1 uV
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = gear2only
lteratio = 10
relref = alllocal
cmin = 0 F
gmin = 1 pS
0 ns, Dreg==1'b0, Xin=1
1 ns, Dreg=x
1 ns, Dreg rises
1ns mclk_150k rises, mclk_150k=x
1 ns, Dreg=1
1 ns, Dreg rises
1ns mclk_150k rises, mclk_150k=1
472 ns, Dreg==1'b0, Xin=1
tran: time = 472 ns (3.15 %), step = 117 ns (780 m%)
472 ns, Dreg=x
472 ns, Dreg rises
703 ns, Dreg=1
703 ns, Dreg rises
tran: time = 1.15 us (7.67 %), step = 150 ns (1 %)
tran: time = 1.889 us (12.6 %), step = 150 ns (1 %)
tran: time = 2.639 us (17.6 %), step = 150 ns (1 %)
2900ns mclk_150k rises, mclk_150k=1
3001 ns, Dreg==1'b1, Xin=1
3002 ns, Dreg=x
3002 ns, Dreg falls
3002 ns, Dreg=0
3002 ns, Dreg falls
tran: time = 3.468 us (23.1 %), step = 150 ns (1 %)
tran: time = 4.218 us (28.1 %), step = 150 ns (1 %)
tran: time = 4.968 us (33.1 %), step = 150 ns (1 %)
tran: time = 5.718 us (38.1 %), step = 150 ns (1 %)
6000 ns, Dreg==1'b0, Xin=1
6001 ns, Dreg=x
6001 ns, Dreg rises
6001ns mclk_150k rises, mclk_150k=x
6001 ns, Dreg=1
6001 ns, Dreg rises
6001ns mclk_150k rises, mclk_150k=1
tran: time = 6.467 us (43.1 %), step = 150 ns (1 %)
tran: time = 7.217 us (48.1 %), step = 150 ns (1 %)
tran: time = 7.967 us (53.1 %), step = 150 ns (1 %)
8700ns mclk_150k rises, mclk_150k=1
tran: time = 8.717 us (58.1 %), step = 150 ns (1 %)
9001 ns, Dreg==1'b1, Xin=1
9002 ns, Dreg=x
9002 ns, Dreg falls
9002 ns, Dreg=0
9002 ns, Dreg falls
tran: time = 9.468 us (63.1 %), step = 150 ns (1 %)
tran: time = 10.22 us (68.1 %), step = 150 ns (1 %)
tran: time = 10.97 us (73.1 %), step = 150 ns (1 %)
tran: time = 11.72 us (78.1 %), step = 150 ns (1 %)
12000 ns, Dreg==1'b0, Xin=1
12001 ns, Dreg=x
12001 ns, Dreg rises
12001ns mclk_150k rises, mclk_150k=x
12001 ns, Dreg=1
12001 ns, Dreg rises
12001ns mclk_150k rises, mclk_150k=1
tran: time = 12.47 us (83.1 %), step = 150 ns (1 %)
tran: time = 13.22 us (88.1 %), step = 150 ns (1 %)
tran: time = 13.97 us (93.1 %), step = 150 ns (1 %)
14500ns mclk_150k rises, mclk_150k=1
tran: time = 14.72 us (98.1 %), step = 150 ns (1 %)
Number of accepted tran steps = 158
Initial condition solution time: CPU = 1 ms, elapsed = 631.094 us.
**** AMSD: Mixed-Signal Activity Statistics ****
Number of A-to-D events: 16
Number of A-to-D events in IEs: 16
Number of D-to-A events: 0
Number of D-to-A events in IEs: 0
Number of VHDL-AMS Breaks: 0