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Problems with a design of an ultra low power AOP
Sep 19^th, 2011, 2:09am

Hi every body,
I'm working on the design of an AOP with 500nA of current supply. My big problem is that when I run Monte Carlo simulation the AC gain decreases of about 80 db. I've tried to increase the effective voltage of transistors but the problem still the same. Is anyone has an idea to how stabilise my AOP without increasing my power consumption?
Ps: it's a typical 2 stage AOP.

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aaron_do Senior Fellow Offline Posts: 1398	Re: Problems with a design of an ultra low power AOP Reply #1 - Sep 19^th, 2011, 2:38am Hi, i'm gonna assume AOP is an op-amp. If you have 80 dB variation, then I guess your DC biasing point is not good. Try running corner simulations, or temperature variations, and check the biasing point. regards, Aaron
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PaloAlto New Member Offline Posts: 6	Re: Problems with a design of an ultra low power AOP Reply #2 - Sep 19^th, 2011, 2:54am You can find the exact run of montecarlo that made the AC gain go down that much. Load that particular run and check the OP. As Aaron says, your OP is most likely wrong.
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raja.cedt

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Re: Problems with a design of an ultra low power AOP
Reply #3 - Sep 19^th, 2011, 4:45am

hello,
ya correct, as the previous guys pointed out your DC bias is very unstable. So check wether you have used correct current mirror design or not. Some times people don't care about chosing mirror transisters size, then many transisters will enter into triod or some other region. First keep every transister Vov and Vdsat around 70mv or at least keep 50mv. Then run the monte carlo sim iteration where you are facing problem and check it's op.

By the way please post schematic.

Thanks.

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HeavyDesign

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Re: Problems with a design of an ultra low power AOP
Reply #4 - Sep 20^th, 2011, 2:52am

Thanks for your answer,
here is the schematic :
and sorry for AOP, I mean by AOP op-amp.
So, yesterday I checked my bias point and it's well biased in typical mode and when I look at the output of the differential pair, my ac gain is correct. it seems that my output stage is wrongly biased.
I'm trying to get the right bias point but if you have any idea I'll be grateful.

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AOP.jpg

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Problems with a design of an ultra low power AOP Reply #5 - Sep 20^th, 2011, 4:59am hello, you have to bias o/p stage with half current so that first stage o/p voltage will be exctly euqal to 2nd stage bias. I feel you have same current in both caes. By looking at schematic i came to this. Thanks,
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aaron_do

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Re: Problems with a design of an ultra low power AOP
Reply #6 - Sep 20^th, 2011, 7:37am

Hi,

I think your problem is that you are simulating the circuit in an open-loop condition. Since this is an op-amp, maybe you should be simulating it in a closed loop configuration. The DC feedback will ensure proper biasing of your output stage. In a closed loop configuration, you can check the loop gain using an stb analysis, but this is not equal to the open-loop gain of the op-amp.

regards,
Aaron

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RobG

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Re: Problems with a design of an ultra low power AOP
Reply #7 - Sep 21^st, 2011, 9:58am

Wow, with lengths in the 100s I hope you are operating at DC or slower ;D

500nA is well within the range of doable and there is nothing wrong with your topology that I can see so it is probably a simulation issue. I'm not sure how much I'd trust those models at those lengths. I would think you could get away with a length of 10u for most of the transistors, especially the diff pair.

On an unrelated subject, you should include the Nwell-to-sub capacitance on the tail if you are going to tie the bulks to that node. I'd just tie it to the power supply.

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RobG Community Fellow Offline Posts: 570 Bozeman, MT	Re: Problems with a design of an ultra low power AOP Reply #8 - Sep 21^st, 2011, 10:27am I'll add that I don't think that 2x cascode is doing much for you with such long lengths. It could be making the leftmost PMOS go linear.
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Lex

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Re: Problems with a design of an ultra low power AOP
Reply #9 - Sep 22^nd, 2011, 12:51am

I share RobG hesitations on the transistor dimensions (especially the modelling). Check your PDK for validity of the models for these lengths. If I were you, I'd split transistors to get a reasonable sizing.

RobG wrote on Sep 21^st, 2011, 9:58am:

...

On an unrelated subject, you should include the Nwell-to-sub capacitance on the tail if you are going to tie the bulks to that node. I'd just tie it to the power supply.

Doing that will definitely destroy your PSRR. And of course lower AC performance in general. Adding a n-well to sub diode to your sim does not take a lot of effort I guess.

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HeavyDesign New Member Offline Posts: 5	Re: Problems with a design of an ultra low power AOP Reply #10 - Sep 22^nd, 2011, 2:04am Hi, Thank you guys for your different ideas . it's true that I can not study the stability of the amplifier in open loop so by now I am trying to study it in a close loop schema but it is not simple.
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RobG

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Re: Problems with a design of an ultra low power AOP
Reply #11 - Sep 22^nd, 2011, 8:28am

Lex wrote on Sep 22^nd, 2011, 12:51am:

I share RobG hesitations on the transistor dimensions (especially the modelling). Check your PDK for validity of the models for these lengths. If I were you, I'd split transistors to get a reasonable sizing.

RobG wrote on Sep 21^st, 2011, 9:58am:

...

On an unrelated subject, you should include the Nwell-to-sub capacitance on the tail if you are going to tie the bulks to that node. I'd just tie it to the power supply.

Doing that will definitely destroy your PSRR. And of course lower AC performance in general. Adding a n-well to sub diode to your sim does not take a lot of effort I guess.

It will not destroy your PSRR since the noise is common mode. It is done all the time. AC performance is actually improved as the cap on the tail node can really mess things up.

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Lex

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Re: Problems with a design of an ultra low power AOP
Reply #12 - Sep 22^nd, 2011, 11:51pm

RobG wrote on Sep 22^nd, 2011, 8:28am:

Lex wrote on Sep 22^nd, 2011, 12:51am:

I share RobG hesitations on the transistor dimensions (especially the modelling). Check your PDK for validity of the models for these lengths. If I were you, I'd split transistors to get a reasonable sizing.

RobG wrote on Sep 21^st, 2011, 9:58am:

...

On an unrelated subject, you should include the Nwell-to-sub capacitance on the tail if you are going to tie the bulks to that node. I'd just tie it to the power supply.

Doing that will definitely destroy your PSRR. And of course lower AC performance in general. Adding a n-well to sub diode to your sim does not take a lot of effort I guess.

It will not destroy your PSRR since the noise is common mode. It is done all the time. AC performance is actually improved as the cap on the tail node can really mess things up.

I don't agree. This circuit is single ended i.e. assymetric. The impedance at your positive input will be different from your negative input (when placing it in feedback configuration), and your impedance at your drain is different.

And your AC performance is worse, as the juction capacitance of a n-well to sub is lowly doped, and hence smaller than the capacitance from n-well to the channel.

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RobG

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Re: Problems with a design of an ultra low power AOP
Reply #13 - Sep 23^rd, 2011, 1:00am

Oh come on, I couldn't even begin to count how many single-ended opamps I've built over the last 19 years with the bulk tied to the supply. The performance hit isn't that much, certainly not anything you could call "destroyed." On the other hand, having a bit fat Nwell cap on a nano-amp opamp with a giant diff-pair is going to make it very interesting, especially if a step input is applied when in a non-inverting configuration.

rg

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Lex

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Re: Problems with a design of an ultra low power AOP
Reply #14 - Sep 23^rd, 2011, 1:59am

In some noncritical environment it does not matter, I agree. But suppose you would use this amplifier in a bandgap circuit, where common mode is of importance. Then your whole point is false. Generalizing is fine by me, but at least specify this.
Or suppose that this amplifier is the critical point for power consumption in a chip since you might have 100's of them in a chip. Then, any arbitrary �gain (lets say 10%) you get from connecting the sourcebulks together is welcome. Note, this is not a technique where you simulate for hours to get an optimal point which is never going to happen IRL. This is a principal way to make it better, and that is the difference. Naturally, as with any design choice, there are tradeoffs.

Anyhow, I have no doubt that you know all of this, but a freshman might not.

PS. I agree that the word 'destroy' was a bit exaggerated, but hey, a good spark was needed for the discussion, right? =)

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