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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › HOw �to declare a �bit

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HOw �to declare a �bit (Read 2256 times)

zahrein Junior Member Offline Posts: 14	HOw �to declare a �bit Sep 29^th, 2011, 12:04am Hi Is this �how �you declare a bit? real d_enable =1b'1; CODE module �measure_voh_vol (pad,data); input pad; //input d_enable; input data; parameter real voh=0.9; parameter real �vol=0.3; real d_enable =1b'1;
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: HOw �to declare a �bit Reply #1 - Oct 7^th, 2011, 7:42am Without thinking too hard about it, I would have said integer d_enable = 1b'1;
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boe Community Fellow Offline Posts: 615	Re: HOw �to declare a �bit Reply #2 - Oct 7^th, 2011, 8:08am In Verilog(-AMS) integers are (at least) 32 bit wide. If you want a single bit you should use a reg/wire. -B O E
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