Hi, so i am trying to convert a 4x4 bit unsigned multiplier into a 5x5 signed multiplier. The way we are to be doing it is that we just have to check the sign bits and 2's complement any number that is most significant bit 1 and 2's complement end products if necessary. My issue is that I can't seem to call the 4x4 bit multiplier in my 5x5 signed multiplier. This is the error:

Error (10170): Verilog HDL syntax error at s_mult5x5.v(19) near text "u";  expecting "<=", or "="

Here is the code of my 5x5 multiplier:

module s_mult5x5(clk, st, mplier, mcand, prod, done);
     input clk;
     input st;
     input [4:0] mplier, mcand;
     output [8:0] prod;
     output done;
     wire x, y;
     
     reg done;
     reg [8:0] prod;

     always @(posedge clk or posedge st)
     begin
     if (mplier[4])
           x = ~mplier[3:0] + 1;
     if (mcand[4])
           y = ~mcand[3:0] + 1;

     mult4x4 u (clk, st, mplier, mcand, prod, done);

     if(mplier[4]^mcand[4])
                 product = ~product + 1;
     end
endmodule
           
           

Hey Ken, thx for responding. After moving it out of the always block it let's me call the function, but now i am getting other errors on my last if block.

Error (10170): Verilog HDL syntax error at s_mult5x5.v(20) near text "begin";  expecting "endmodule"
Error (10170): Verilog HDL syntax error at s_mult5x5.v(21) near text "^";  expecting ".", or an identifier

Here's the new code:
module s_mult5x5(clk, st, mplier, mcand, prod, done);
     input clk;
     input st;
     input [4:0] mplier, mcand;
     output [8:0] prod;
     output done;
     
     reg done;
     reg [8:0] prod;

     always @(posedge clk or posedge st)
     begin
     if (mplier[4])
           mplier[3:0] = ~mplier[3:0] + 1;
     if (mcand[4])
           mcand[3:0] = ~mcand[3:0] + 1;
     end
     
     mult4x4 u (clk, st, mplier[3:0], mcand[3:0], prod, done);

     if(mplier[4]^mcand[4])
                 prod = ~prod + 1;

endmodule

Hey Ken,

I apologize for asking basic questions while I am missing some basic concepts of verilog since I never really learned it. But I do understand what you said, thank you for the clarification. I will be able to figure it out keeping that in mind when writing hte code. Perhaps you can help me with a code that my teacher wrote. I wrote a testbench to test the code, but am only get xxxxxxxx for the output. I tried tracing through the code to see what the signals are and can't find any errors, but then again I am not an expert in it. Here is the code:

module mult4x4(clk, st, mplier, mcand, prod, done);
     input clk;
     input st;
     input [3:0] mplier, mcand;
     output [8:0] prod; //added
     output done;

     reg done;
     reg [3:0] pstate,nstate;
     reg [8:0] prod;
     
     parameter s0=4'b0000, s1=4'b0001, s2=4'b0010, s3=4'b0011;
     parameter s4=4'b0100, s5=4'b0101, s6=4'b0110, s7=4'b0111;
     parameter s8=4'b1000, s9=4'b1001;

     reg [8:0] ACC; //accumulator
     //reg M=ACC[0]; //M is bit 0 of ACC; could use 'define
     wire M;

     assign M = ACC[0];

     always @(posedge clk or posedge st)
           if (st) pstate = s0;
           else pstate = nstate;

     always @(pstate) //state transition
           case (pstate)
           s0: if(st) nstate = s1;
           s1: if (M) nstate = s2; else nstate = s3;
           s2: nstate = s3;
           s3: if (M) nstate = s4; else nstate = s5;
           s4: nstate = s5;
           s5: if (M) nstate = s6; else nstate = s7;
           s6: nstate = s7;
           s7: if (M) nstate = s8; else nstate = s8;
           s8: nstate = s9;
           s9: nstate = s0;
           endcase
           
     always @(pstate) //Output (Action)
           case (pstate)
           s0: begin
                 ACC[8:4] = 5'b00000;
                 ACC[3:0] = mplier;
                 end
           s1: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
           s2: ACC = {1'b0, ACC[8:1]};
           s3: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
           s4: ACC = {1'b0, ACC[8:1]};
           s5: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
           s6: ACC = {1'b0, ACC[8:1]};
           s7: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
           s8: ACC = {1'b0, ACC[8:1]};
           s9: begin
                 done = 1'b1;
                 prod = ACC;
                 end
           endcase
endmodule