hello,
i have done some 50% duty cycle correction at this frequency, there i used to compare avg value of the clock by vdd/2 and drive the feedback loop. may be you can try by comparing .25*vdd. Any kind of fedback is welcome. You can find the fig for understanding.

One more thing why you need 25% duty cycle?

Thanks,
Raj.

Guess this depends on the technology.

Over process the high Vt corners will limit how much current you can slew for the capacitance of the device plus whatever load you are driving.

You may find you must burn a lot of current to meet the rise/fall times for the pulses you want to generate.

Hi Ricky,

This should be doable - you can use a divide by 2 circuit with LO as input (standard cell or TSPC) and logically AND it with the LO (after inserting delay to take care of propogation delay through the divide by 2) - along the lines of Rfcooltool's idea.

A different approach:

Use different phases of a clock.

For example - Stay with the 5GHz clock, and set up a 4 phase clock at this rate. You now have an "edge rate" at the 25% duty cycle points. Combine the signals to get the needed control signals.

You may need to use current steering logic in some places to get the higher frequency signals.