vp1953 wrote on Oct 17th, 2011, 12:02pm:Hi Ricky,
This should be doable - you can use a divide by 2 circuit with LO as input (standard cell or TSPC) and logically AND it with the LO (after inserting delay to take care of propogation delay through the divide by 2) - along the lines of Rfcooltool's idea.
Thanks vp1953.
But the FO4 delay in 130 nm Technology is 65 ps. So if you are getting 25 % duty cycle at 5 GHz Rail-to-rail (1.2 V - 0 ) clock means:- Your duty cycle period (ON time) will be only 50 ps. So the clock has to rise and fall within 50 ps to give you 25 % duty cycle).
is it possible without using INDUCTOR ?
Thanks
-ricky