Hi folks,

To avoid running into the "hidden state" errors in SpectreRF, i used the track-and-hold model (from Listing2 by Ken Kundert's document titled "Hidden State in SpectreRF").   Basically, i had a mixed-signal macro model consisting of some analog circuits and digital feedback control (modeled in behavioral Verilog-A) in a closed-loop configuration.  

A few "analog-type" registers (state element) were originally declared in my behavioral Verilog-A and SpectreRF complains about them as being "hidden state".  So, I ended up replacing each and every register with the track-and-hold model.  I verified that the functionality of the standalone Verilog-A model before and after the change is the same.   The good thing is that SpectreRF PSS runs to completion successfully.   The bad thing is that i am seeing oscillations in my output voltage, indicating that the oveall system is unstable.  

The PAC phase plots also seem to indicate that the phase margin is close to 0 deg.  (phase drops to 180 deg. at very low frequency).
This leads me to wonder if the track-and-hold circuit somehow adds a low-frequency pole to the small-signal response of my original loop-gain transfer function.  

This track-and-hold circuit has 2 phases, i.e. sampling and hold.  During sampling phase, a pole is formed by Ron and C.  Typically, this pole is located at fairly high frequency since Ron is small and C is around 1nF or so.    During hold phase, another pole is formed by Roff and C.   It is this pole which worries me since Roff is very large (~10^12 ohm) and C=1nF, meaning that this pole is located at very low frequency.  

So,  it appears to me that the track-and-hold circuit actually changes the frequency response of my overall system due to its low-pass filtering action.

The following are my questions:
1.  How can i modify the track-and-hold model so that its poles will be moved to higher frequency ?

2.  SpectreRF supports differential operators (idt, ddt) and Laplace function.  So, modeling continuous-time filter in s-domain is easy.   But, the trouble comes when we model discrete-time (digital) filter in z-domain because SpectreRF does not support the Z function and any register-like constructs in Verilog-A.  

So, i am sure people have run into this kind of situation before and really appreciate if any of you can shed some light.

Thanks.

-albert

Hi Ken,

The following is the block diagram of my whole system in closed-loop
configuration.

 
                 +=================+
      vin => |   analog circuit                |
         ==> | (feedforward stage)       | ----------> vout
        |       +=================+         |
        |                                                           |
        |                                                        ADC
        |                                                           |
        |         +=================+       V
        |          |  Digital Filter                  | <-----
     DAC <--- | (feedback control)         |
                   | (modeled in Verilog-A    |
                  +=================+              

My digital filter contains a few registers (modeled in time domain) and in order to run SpectreRF, i replaced these registers with your track-and-hold model.

-albert                        

After replacing my discrete-time filter with the equivalent continuous-time filter, the PAC loop gain magnitude and phase plots are correct and consistent with that from my Matlab sim.

So, this leaves 2 possibilities.  Either i am not modeling my discrete-time filter correctly -or- for some reason, the PAC signal cannot get through certain block in my closed-loop system and the PAC amplitude at the output is zero, resulting in a lower DC gain.

1. For possibility #1, verified that the unit-step response of my digital filter using ideal sample-and-hold is the same as that using "behavioral" registers in Verilog-A.  Also, ran PAC on the standalone digital filter using ideal sample-and-hold and the PAC magnitude and phase plots are consistent with those from my Matlab sim.

2. For possibility #2, since the output of my digital filter directly feeds into a PWM modulator (with a periodic sawtooth waveform) generating a 50% duty cycle in steady state,  i wonder if the gain reported by PAC is also scaled by the duty cycle.    It is because SpectreRF operates on continuous-time signals and for sampled-data system, SpectreRF is computing the Fourier coefficients and scale them by the duty ratio.  Hence,  the fundamental Fourier coefficient will not be 1.

Any clues or comments ?

Hi Ken,

Thanks a lot for your comment.   However, my PAC analysis is observing the output voltage of my pwm switching converter, i.e. the small-signal gain is d(Vout)/d(Vfb), where Vout is the output voltage of the switching converter and Vfb is the feedback voltage.

To run PAC, I inserted a vsource (dc=0 pacmag=1) between the output voltage and the top feedback resistor which is along the feedback loop.

The interesting thing is that when i replaced only the discrete-time filter with the "equivalent" continuous-time filter, everything looks correct.  But, as soon as I plug my discrete-time filter back into my closed-loop system, the DC gain drops by approx. 60B and the single dominant compensated pole is shifted out.    In both cases, the output of the filter directly feeds into the PWM modulator.

On the other hand, i also ran PAC on the discrete-time filter alone and the PAC magnitude and phase plots are correct.  I even ran the unit-step response on this filter and the result is the same as that from my Matlab simulation.   So, i am quite confident that my discrete-time filter is modeled correctly.

I guess I am still trying to get down to the bottom of this issue.   I really appreciate if you can shed some light here....perhaps,  I did something stupid here.

Hi Ken,

Please see the attached pdf file for my closed-loop system, consisting of an idealized PWM switching regulator with a digital feedback network.

In the diagram, S/H is the ideal sample-and-hold model i borrowed from your document.

As you can see, there are actually 2 loops here, namely an outer loop with a feedback resistor divider and an inner loop within the digital filter.   Does PAC support this kind of two-loop system ?    To order for PAC to do its job right, what changes do I need to make in my closed-loop model ?

Originally, i coded everything under the digital filter in one single Verilog-A model.  To enable debugging, i flatten it out now, therefore exposing the smaller feedback loop within the filter.

I really hope this diagram gives you a better idea of my problem.

Thanks in advance.      

1. The frequency of the S/H clocks and PWM are the same which is 1MHz.  In other words, phi1, phi2 and the sawtooth waveform (as shown in my diagram) are running at 1MHz.

2. The function of the logic is a simple non-overlapping clock generation which prevents both switches (in the switching regulator) from turning on simultaneously.  It is at the transistor level.

To summarize, my simulation model is a mixed-mode model, consisting of the following components.

a.  analoglib->vcvs  
    gain = 1  for subtractor
    gain = a or b   for multiplier
    gain = 1000   for PWM modulator

b.  your Verilog-A model  for S/H

c.  analoglib->R, L, C   for RLC passive components

d.  analoglib->switch  for ideal switches in switching regulator

e.  digital_lib->buffer, inverter, etc.   for the digital logic (at transistor level)

f.  analoglib->vdc   for PAC source (dc=0  pacmag=1)

g. analoglib->vsource  for all the voltage sources, e.g. sawtooth waveform.


Please feel free to let me know if you have any further questions.