Hello,

I described a RAM in verilog, and in the top level I instantiated 8 block of the same RAM. I have to initialize them by a different set of data... so I want to use the command "readmemb" at top level but I don't know the correct syntax or if this is possible

---------RAM code-----------

module ram_64B(clk, en, write_en, data_in, data_add, data_out);
     input clk, en, write_en;
     input [7:0] data_in;
     input [5:0] data_add;
     output [7:0] data_out;
     
     parameter RAM_WIDTH = 8;
  parameter RAM_ADDR_BITS = 6;
 
  //(* RAM_STYLE="{AUTO | BLOCK |  BLOCK_POWER1 | BLOCK_POWER2}" *)
  reg [RAM_WIDTH-1:0] ram [(2**RAM_ADDR_BITS)-1:0];
  reg [RAM_WIDTH-1:0] data_out;

  wire [RAM_ADDR_BITS-1:0] data_add;
  wire [RAM_WIDTH-1:0] data_in;

  always @(negedge clk)
     if (en)
           begin
        if (write_en) begin
           ram[data_add] <= data_in;
           data_out <= data_in;
        end
        else
           data_out <= ram[data_add];
     end
           
endmodule

---------Top level-------------------

ram_64B tm_filt1 (clk, en_ram, 1'b0, data_in_tm_filt1, data_add_tm, data_tm_filt1);
ram_64B tm_filt2 (clk, en_ram, 1'b0, data_in_tm_filt2, data_add_tm, data_tm_filt2);
ram_64B tm_filt3 (clk, en_ram, 1'b0, data_in_tm_filt3, data_add_tm, data_tm_filt3);
ram_64B tm_filt4 (clk, en_ram, 1'b0, data_in_tm_filt4, data_add_tm, data_tm_filt4);
ram_64B tm_filt5 (clk, en_ram, 1'b0, data_in_tm_filt5, data_add_tm, data_tm_filt5);
ram_64B tm_filt6 (clk, en_ram, 1'b0, data_in_tm_filt6, data_add_tm, data_tm_filt6);
ram_64B tm_filt7 (clk, en_ram, 1'b0, data_in_tm_filt7, data_add_tm, data_tm_filt7);
ram_64B tm_filt8 (clk, en_ram, 1'b0, data_in_tm_filt8, data_add_tm, data_tm_filt8);

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Thank you