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EEPROM exposure to XRAY (Read 8995 times)
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EEPROM exposure to XRAY
Oct 13th, 2011, 11:14am
Hello Folks,

We have an interesting problem. We have a System In a Package (SIP) with a DSP whcih we designed and an EEPROM in packaged in one hybrid. The DSP when powers up, it load data from EEPROM. The part is failing at 40C in that the DSP is unable to get the data from EEPROM. We had both EEPROM and DSP pass our wafer test.

In trying to debug this issue, we exposed the SIP pacakge to XRAY and when we tried to power the part now it fails at 25C and above upto 60C. The part properly boots up at 20C and below. There seems to be a shift in the temperature for failure to read from EEPROM post XRAY exposure.

Does anyone have experience with EEPROMs in knowing whether exposure to XRAY would damage anything in EEPROMs e.g. timing etc.

Note the DSP provides supply to EEPROM whcih we measured (as there is a pin IO on the final package and is sufficiently high).

Any suggestions?

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Re: EEPROM exposure to XRAY
Reply #1 - Oct 13th, 2011, 1:48pm
depends on the EEPROM technology used, talk the the vendor of that chip.
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Jerry Twomey
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Re: EEPROM exposure to XRAY
Reply #2 - Oct 14th, 2011, 9:09am
Considerable doses of radiation can cause Vth of MOS transistors to shift, thus affecting the performance of any circuit.
As loose-electron already pointed out, you should ask the vendor of you memory for specifics (such as maximum dose) if you need to expose your circuit to radiation.

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Re: EEPROM exposure to XRAY
Reply #3 - Nov 11th, 2011, 10:44pm
I agree with the other posters, however, there is another thing that occurs when you subject EEPROMs to radiation - the charge on the floating gate can be degraded.

Radiation has a certain amount of energy associated with it (the amount depends on a few factors that escape me at the moment.) Well, this small amount - on the order of a few eV is enough to cause tunneling and thus affect the charge. It sounds like this could have also led to your part now working at a lower temperature only, in addition to Vt threshold changes, etc. The eV level required to upset the floating-gate charge is based on the tunnel oxide thickness; the thinner the oxide, the less energy required to affect the floating gate charge.

We generally don't our EEPROMs to be irradiated...

Joe W.
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