sean.geng wrote on Oct 17th, 2011, 2:50am:and i want to ask everyone that, according to my thoughts, the speed up circuit will accelerate settling behavior whenever the output of OPAMP increases or decreases. however, the simulation results just prove it is right when the output of OPAMP increases. and when in decreasing condition, it will be slower than without the circuit.
so, can anybody tell me what's wrong?
I agree that the speed should increase either way. Maybe it is some problem in the biasing? Maybe it is some speed related issue? Did you check what happens to the 'gate' voltage in your design when going up and down? And check the gatevoltages of the transistors driving that node (the PMOS and NMOS).
On a side note, maybe u could provide a clear schematic, because the text and numbers are barely readable. At least it would make it clear whether u use long/short devices and so on.