Raj,
Yes I am talking about serial IO and simulating ONLY RX.
Assuming the PRBS data coming from TX with the data freq F and F/2.
I am changing the PLL settings to have throughput clock to sample the data at frequency F and F/2. Since the CDR is shut down, I am changing the clk frequency on-the-fly as a stimulus.
I am changing the data freq from F to F/2 because the serial IO has to support the legacy and some customers may want to use at different data rate i.e. half rate/quarter rate etc. Not only this, one may need to vary the data rate as the part of testing mode. I want to study the supply noise and jitter specs because of change in frequency rate.
The VCO is LC based but we are not concerned of power consumption.
Please let me know, if you have further questions to answer my question
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Thanks