Hi,

I am designing a switched capacitor filter in 250um technology, 1v operating in weak inversion.

1.I want to know how to size the switches.

2. I want to use atleast 2Lmin because short channel affect causes Ids to get saturated very early to low values in case of Lmin.

3. I am going for NMOS switches due to supply constraint of 1v.

4. What should be the widths? I am not able to trade off resistance v/s parasitics. What is the technique to size it?

Thanks,

hello mixed_signal,
A switch has to be in triode always to give less on resistance.
In theory lenght has to be as low as posb to give less Ron, but due to limited supply you have to chose a Lmin based on Vth (typically it varies with L, due to short channel effect it will reduce with length but to reverse short channel effect or retrogate channel profile it may increase with decres in lenght) so simulate and compremise some where. Where as width can be chosen from on state voltage drop, which will be decrease with increase in the width but higher will impact your switch cap settling. So i sugget you to put in siimulation get some set of L and W, now simulate Switchcap.

But one question is you are working with 250nm tech, i guess you will have min of 1.8 supply(up to my knoledge on TSMC tech).

Thanks,
Raj.

Thank you raja.cedt and rajkumar palwai for you valuable replies.

Thank you loose electron.

I have a basic doubt. I am simulating an NMOS switch. Suppose I have tied gate to vdd=1v (switch is on), source to a capacitor and drain to 800mv. I want to see the maximum output voltage of my switch i.e. the capacitor voltage. The expected value is vdd-vth , right? But when I ran a DC simulation i found voltage at the capacitor is always equal to the applied drain voltage. How can I simulate it?

Thanks

hello mixed_signal,
yes you are correct, in theory drain voltage will stop at vin-vth, but in .DC  simulations may be leakage will get you the Vin many times (if you have enough time and dc simulation means steady state simulation) or think like mosfet and cap is like RC low pass filter and when o/p goes near to vin-vth, mosfet R increase like any thing and time constant will increase.

Thanks,
Raj.

hello mixed_signal,
make sure that you have less Vds compared to Vgs (this is very common case because for switched you gives full vdd to gate while turn on) and i haven't done any thing special to keep in triode.

regarding your last question, yes they do exchange terminals, but they are in triode, vds is really low so it doesn't matter which is S and D.

Thanks,
Raj.

consider a pass gate configuration

NMOS in parallel with PMOS

NMOS good for low voltages, PMOS good for high voltages.

For clock boosting methods see:
inst.eecs.berkeley.edu/~ee247/fa06/lectures/L19_f06.pdf

hello rajkumar,
are you talking about gain boosting technique, where charge pump will be used to get more supply ..

Thanks,
Raj.