Praveen,
any leakage path at the gate of M7 will take the steady state node voltage to the extremes eventually and hence the circuit doesn't work.

I mean, at the steady state the average value of the M7 gate voltage would be either '0' or 'vdd' depending on whether the leakage to gnd is strong or leakage to vdd is strong.

U can simulate a simple example case. Put 2 caps in series and give 2 transient signals at the 2 ends. Then connect a big resistor (eg:1e12) at the centre node to gnd/vdd to model the leakage and see the o/p waveforms.

rajkumar palwai wrote on Nov 1^st, 2011, 4:23am:


You did NOT understand what I mean to say.
What do you think the leakage impedance will be ?? Will it be such that it will leak the sizable amount of charge from the CAP before the refresh cycle ??

if that you think, then probably switch-CAP circuit would NOT have existed !!

Ricky Chen wrote on Oct 31^st, 2011, 11:58pm:


None of us can read minds.
You never said anything before about this.
Please define your probably correctly in the
future, and do not assume we have the capability
read your mind from the other side of the planet.

My mind reading capabilities are limited to under a 300km range.

loose-electron wrote on Nov 1^st, 2011, 3:53pm:


Hello Loose-Electron

After knowing that it is a switch-cap CMFB, do you have any answer to my question ? How DC f/b is NOT in the circuit ?

Sorry for trying to read people's mind.
Thanks for letting the forum know about your reading CAPABILITY

Lex wrote on Nov 2^nd, 2011, 2:31am:


thanks a Lot !! Alexander

Can you please explain why it will have better (large signal) common mode rejection ?
You may point to any literature which actually explains this large signal CM behavior in CMFB circuit

Maybe Ricky should change his chance his avatar to Wilma so I can tell him from loose e- (as in loose e, I'm home).

I don't know a ton about cap cmfb, but the circuits I've seen switch both sides of the cap to reference points during a reset cycle. This allows a voltage drop across the caps to the fb device and the CM output to be biased at any level desired. If resistors were used there would be no DC drop and the either the fb device or the diff pair would be linear except within a very small range of input common mode bias with this particular topology. (Although a dc current could be injected at node P to level shift the output common mode level.)

You'd like the FB device to supply only a small current to keep the common mode gain small, especially for increased stability (IE the parallel DC tail source supplies most of the current). The danger of this is that if mismatches cause the parallel DC tail current to be more than the PMOS currents the fb device will be completely off and the output will be pulled low.

Low CMFB gain also means the common mode output will deviate a larger amount from ideal since the FB device will need more gate drive to make up for mismatched tail/load currents.


addendum... I'm pretty sure this circuit is meant to be reset as opposed to using resistances. The resistances are not needed: one could use simply use two NMOS FB devices: both drains tied to the tail, and the first/second gates tied to the left/right outputs respectively.