Hello,
I have a basic question about DAC SFDR.

I modeled an ideal 16bit dac in verilog-a, I apply an ideal sine wave of 400MHz to an ideal 16bit adc, the adc drives the dac. When I use a fourier transform of the output of the dac, the clock rate is 8GHz, I get -92dB THD. However, if I drop the clock rate to 1.6GHz the THD drops to -6.9dB. I am plotting the 1st 16 harmonics.

When I look at ADI, Maxim, NXP etc their input data rate is 1/4 of the clock rate but their dac( which are not ideal) are showing much better results

any help will be greatly appreciated
thanks analog2001

hello analog2001,
What's your Question, is it about SFDR or THD? SFDR is about largest harmonic and THD is about all harmonics

Any how it's very common to observe SFDR drop at higher sampling rate due to several frequency dependent degradation like o/p impedance of the tail current source, delay variation to current steering switch. In general people are intersted SFRD at frequencies near to nyquist rate.

Thanks,
Raj

Hi Analog2001,
The SFDR is the difference in dB between the fundamental and the higher harmonic. Thus, the SFDR is generaly higher than the THD.