analog2001
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Hello, I have a basic question about DAC SFDR.
I modeled an ideal 16bit dac in verilog-a, I apply an ideal sine wave of 400MHz to an ideal 16bit adc, the adc drives the dac. When I use a fourier transform of the output of the dac, the clock rate is 8GHz, I get -92dB THD. However, if I drop the clock rate to 1.6GHz the THD drops to -6.9dB. I am plotting the 1st 16 harmonics.
When I look at ADI, Maxim, NXP etc their input data rate is 1/4 of the clock rate but their dac( which are not ideal) are showing much better results
any help will be greatly appreciated thanks analog2001
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