Designer’s Guide Community

New Member

Offline

Posts: 5

why passive adder are sensitive to itself parasitic capacitance in DT SDM
Nov 18^th, 2011, 2:15am

hi, all

I just figue out the passive adder is affected by comparator input node parasitic capacitor. The comparator input node voltage is attenated.
But some papers write passive adder are sensitive to itself parasitic capacitance. I am not clear what is mean. Am I missing something more important to consider?

thanks a lot!

L.W

Back to top

IP Logged

raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: why passive adder are sensitive to itself parasitic capacitance in DT SDM Reply #1 - Nov 18^th, 2011, 2:57am hello, could you elobarate more, it's difficult to get answers for this kind of Questions, please attach some related stuff if posb. Thanks, raj.
Back to top	IP Logged

lawrence.W

New Member

Offline

Posts: 5

Re: why passive adder are sensitive to itself parasitic capacitance in DT SDM
Reply #2 - Nov 18^th, 2011, 5:40am

Hi, raj

Thanks for your reply.

The attached is schematic. The capacitor adder is made of C1, C2,C3. Cp is parasitic cap of quantier that attenuates the quantizer input voltage. I am not clear the capacitor adder's parasitic caps effect. As I consider, the bottom plate parasitic caps of C1, C2,C3 are not big deal. The top plate parasitic caps also attenuate the quantizer input voltage just like Cp. Am I missing other issue about these parasitic caps?

Thanks

L.W

Back to top

SCH.pdf

IP Logged

loose-electron

Senior Fellow

Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California

Re: why passive adder are sensitive to itself parasitic capacitance in DT SDM
Reply #3 - Nov 18^th, 2011, 9:41am

The circuit shown will have problems with parasitics as part of the capacitors, and the switches also not being ideal, (Both RC time constants and charge losses through the parasitics of the switches.)

Plus noise issues, but I suspect the RC parasitics and non ideal switches will be the big problem.

THe devices will work , but they have limitations.

Back to top

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

IP Logged

lawrence.W

New Member

Offline

Posts: 5

Re: why passive adder are sensitive to itself parasitic capacitance in DT SDM
Reply #4 - Nov 18^th, 2011, 7:14pm

hi. loose-electron

thanks for your reply.

As your reply , RC parasitics is problem. But the problem puzzling me is whether capacitor adder parasitics has same effect as Cp for charge loss if switch is ideal. Can I consider these capacitor adder parasitics as Cp. Then the autozer can be applied to reduce the Cp and capacitor adder parasitics effect.

thanks

L.W

Back to top

IP Logged

loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: why passive adder are sensitive to itself parasitic capacitance in DT SDM Reply #5 - Nov 19^th, 2011, 5:55pm What is Cp? What is the "autosizer" that you mention?
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

lawrence.W New Member Offline Posts: 5	Re: why passive adder are sensitive to itself parasitic capacitance in DT SDM Reply #6 - Nov 20^th, 2011, 7:38pm hi, the Cp is quantizer input node parastic cap. the autozero can be applied to the comparator to reduce offset. thanks L.W
Back to top	IP Logged

loose-electron

Senior Fellow

Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California

Re: why passive adder are sensitive to itself parasitic capacitance in DT SDM
Reply #7 - Nov 21^st, 2011, 2:11pm

ok, understood -

suggest making the circuit such that when it "zero's out" that the decision circuit at the end be fed back around itself so that it precharges the Cp, as shown in red in your drawing, to the switching point. That way your adder circuit only has to determine above/below the trip point of the non-linear decision element.

From what I can tell you are just trying to do a summation such that you determine if you are above-below a decision point, correct?

Back to top

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

IP Logged