Terrible circuit architecture!

Due to the Vcm source follower (you circled it) the input differential pair is not getting their high impedance common mode rejection from a current source below the differential pair. It has a source follower driving it, and the input is no longer truly differential, rather it is now (sort of ) complimentary.

Generally you will control common mode by adjusting the active load, or the common current source. This method I would expect will make common mode rejection worse.

Strange methods to say the least!

hai - The circuit had me baffled at first since I didn't realize it was a dual diff.  However, I believe it's a legit circuit: the source followers are used to keep the total gm constant. This is helpful because the total gm contribution of the two diff pairs would change over the input common mode range, being 2x the value when both pairs are on when the input is in the middle of the common mode range.

It reminds me of a circuit published in the red rag, probably in the mid/late 90's.

Here is how I remember it working. 1) When Vin > VCM the PMOS source follower shunts all of the tail current away from the PMOS diff pair and only the NMOS diff pair is on. 2) When Vin < VCM, the current is shunted away from the NMOS pair, leaving the Pdiff on. 3) When Vin = VCM both diff pairs are one, but at a fraction of the current. The fraction is determined by the relative sizes of the source follower and diff pair fets.

So in all 3 cases of input common mode value the gm remains about the same (if the source followers are sized properly). Thus when it is used on both input pairs the large signal common mode rejection is actually increased. I expect the small signal CMRR is still good at the midpoint because as the current is shunted away from one pair, it is added to the other.

rg

Jerry, maybe I'm wrong but is not the idea with the two Vcm source followers to turn off one of the differential pair. For a high input common mode the top diff stage will work ok since the Vcm source follower will get a low Vgs and is turned off. For a low input common mode the differntial pair is turned off. In the last case to bottom stage is active.

But maybe the circuit is crap anyway in the middle where both stages are avtive

raja.cedt wrote on Nov 22^nd, 2011, 3:29am:

Raj - I didn't mean to say it was better at midrail, just that it was still good (I don't know for sure - but "eyeballing" the circuit I think it should be acceptable). The reason is that as one source follower (SF) shunts current, the other SF is debiased by approximately the same amount, thus the combined top+bottom tail current is about the same. Depending on how you sized the SFs you could optimize CMR or constant gm.

Hai should be aware that mismatched offsets in the diff pairs gives dual diffs bad CMRR. That is to say that when input is low, the offset is from the pDiff, and when the input is high the offset is from the nDiff. Thus the difference in offset results in an output voltage error that is dependent on input common mode. I expect that this error is at least as large as the one caused by the SFs.

raja.cedt wrote on Nov 22^nd, 2011, 3:29am:


At first glance the CMFB looks like it will work to me. Isn't it controlling the active load? At any rate, I bet there is a common-mode glitch when the input passes through midrail since the total tail current will change. However, it will change a lot less than if no SFs were used. In that case one of the tail current sources would completely shut off as the input approached the rails.

One other thing that I see that will help CMRR - note how the diff pair loads are created by mirroring a fraction of the tail current. If I understand the circuit, this would mean that tail current changes aren't "folded" into the output stage. Thus, to first order, a change in tail current will not change the current in the output stage.

rg

hai wrote on Nov 22^nd, 2011, 7:53am:

Hai - the floating current source provides the gate voltage biases for the output stage. I think it is a misnomer to call it a current source in the configuration shown as it doesn't determine the current that flows through its terminals.  The Hogervost paper that I linked uses that topology as an actual current source to bias the opamp in addition to providing the bias for the output stage. It is well worth the time to understand how this "floating current source" bias works.