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chandu28

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DRAM DESIGN
Nov 29^th, 2011, 1:28am

Hello guys,
Iam M.S.Chandra Sekhar currently working(mtech-project) in the field of memory design and it is called "Design of 4Kb DDR SDRAM". I am simulating this in Design Architect (Mentor Graphics).For this project I started with DRAM design and I am stuck with it. could anyone please help me out. Actually the problem is with where to connect the refresh circuit. The order is like this (as I have used)sense amplifier,isolation circuit,cell,refresh circuit,write driver circuit. and I have connected the refresh circuit like a loop to the bitline and by using the pattern Iam running the circuit. The output Iam getting is both distorted and leveled up.
awaiting your reply....

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: DRAM DESIGN Reply #1 - Nov 29^th, 2011, 3:56pm show a schematic please?
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chandu28 Junior Member Offline Posts: 21 vellore	Re: DRAM DESIGN Reply #2 - Nov 29^th, 2011, 8:03pm this is the schematic with complete blocks...can you tell me if all the connections were made correct or not.... thank you
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: DRAM DESIGN Reply #3 - Nov 30^th, 2011, 11:19am Oh, perfectly connected! Very difficult to tell whats what and all that. Suggest you work on better formulation of the question here, can not really tell what you are doing from that drawing.
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AnalogDE Senior Member Offline Posts: 137	Re: DRAM DESIGN Reply #4 - Nov 30^th, 2011, 4:11pm Start with a bit-slice and get that working and understood. After that, then you can figure out how to draw the array schematics.
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chandu28

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Re: DRAM DESIGN
Reply #5 - Nov 30^th, 2011, 9:17pm

actually this is the schematic of a 1 row DRAM design each block is working individually starting from the top sense amplifier,isolation circuit , cells(row of cells) write driver circuit refresh circuit and at he end column decoder...
we know that the main problem in any design is the connections to various blocks i dunno where the mistake is... thats what is my question sir...

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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: DRAM DESIGN Reply #6 - Dec 1^st, 2011, 12:04pm hello chandu, is your refresh ckt working fine, means is it able to write what it have read from the cell in the given time? refer wste and harris digital design he has pointed out many common mistakes... Thanks, Raj.
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loose-electron

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Re: DRAM DESIGN
Reply #7 - Dec 1^st, 2011, 2:23pm

chandu28 wrote on Nov 30^th, 2011, 9:17pm:

actually this is the schematic of a 1 row DRAM design each block is working individually starting from the top sense amplifier,isolation circuit , cells(row of cells) write driver circuit refresh circuit and at he end column decoder...
we know that the main problem in any design is the connections to various blocks i dunno where the mistake is... thats what is my question sir...

OK, then suggest you start by using the blocks to build and simulate as you build parts of the schematic until the response is not as expected.

Divide the problem and understand it as you go.

Also, if you think there is an unexpected loading effect someplace you may want to either monitor currents in connections, or insert ideal voltage to voltage buffers in lines to determine where the loading problem is.

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chandu28

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Re: DRAM DESIGN
Reply #8 - Dec 1^st, 2011, 7:19pm

raja.cedt wrote on Dec 1^st, 2011, 12:04pm:

hello chandu,
is your refresh ckt working fine, means is it able to write what it have read from the cell in the given time? refer wste and harris digital design he has pointed out many common mistakes...

Thanks,
Raj.

hello Raj,
Yes it is I just gave a random pulse with 1v p-p and vdd to the refresh circuit as 5 v p-p with pattern and I got the result exactly as I expected...

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chandu28

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Re: DRAM DESIGN
Reply #9 - Dec 1^st, 2011, 7:25pm

loose-electron wrote on Dec 1^st, 2011, 2:23pm:

OK, then suggest you start by using the blocks to build and simulate as you build parts of the schematic until the response is not as expected.

Divide the problem �and understand it �as you go.

Also, if you think there is an unexpected loading effect someplace you may want to either monitor currents in connections, or insert ideal voltage to voltage buffers in lines to determine where the loading problem is.

sure sir i get to it right away and since Iam connecting the bit and bitbar lines so close will there be any capacitance effect??? and also can we check sense amplifier individually? because Iam not getting proper swing too.... �:)

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: DRAM DESIGN Reply #10 - Dec 2^nd, 2011, 12:06pm If all the individual peieces work as expected - Isolate the parts using voltage to voltage buffers. That will teach you if its a loading issue.
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chandu28 Junior Member Offline Posts: 21 vellore	Re: DRAM DESIGN Reply #11 - Dec 2^nd, 2011, 10:20pm loose-electron wrote on Dec 2^nd, 2011, 12:06pm: If all the individual peieces work as expected - Isolate the parts using voltage to voltage buffers. That will teach you if its a loading issue. Sir, Can you please be more elaborate???
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loose-electron

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Re: DRAM DESIGN
Reply #12 - Dec 3^rd, 2011, 7:34pm

you have the design of several different pieces in your system.

all of them should have been simulated and designed to work as expected

after that, you have connected them together and something is broken.

Correct so far?

If you use a "voltage to voltage" converter in SPICE/Spectre with G=1 on any and all of the connections between boxes, you should be able to get
the boxes functioning again because now the boxes no longer interact or load each other down.

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chandu28 Junior Member Offline Posts: 21 vellore	Re: DRAM DESIGN Reply #13 - Dec 3^rd, 2011, 7:48pm yes sir you are right...by then I can find the fault location....I will try it sir...
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: DRAM DESIGN Reply #14 - Dec 4^th, 2011, 12:31pm not a problem, happy to help, Jerry
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