I found out the error sir ... its the decoder which I have used... its giving 2v output when I give 11 as input and nearly 1 for other 3 inputs.... can you suggest me some which can give equal outputs???  :)

and also the swing is too low please see the pictures

Is the fault in the circuit, or due to the load on the circuiit. (see prior suggestion on buffers to isolate)

start there.

The output of the inverter is probably attenuating the signal, the two devices ar both trying to pull the node in different directions. The result is attenuation or voltage division depending on the size of the transistor involved.

Which device do you want to provide the most signal?

That one should use bigger W/L transistors.

Usually 2 inverter latch structures have small W/L devices so another device with bigger W/L transistors can flip the latch back and forth.

Back to back inverters will act like an SR latch, if you
drive the device properly.

It is a memory device with the driver removed.

When one side or the other is forced high-low the inverters function as inverters.

You really need to do some research and reading on this subject.

http://technav.ieee.org/tag/8571/sdram
http://en.wikipedia.org/wiki/Static_random-access_memory
http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/4/4317684/04317699.pdf?arn...

Start there. Also search for vendors who
make SDRAM chips and read their documentation.

The sense amplifier that you have may not have the needed gain, it is a single logic inverter.

More gain, and a way of matching the center null point
(average of Vmax, Vmin) of the holding cell to gin amplifier are needed.

Maybe 3 inverters in series would be sufficient, perhaps a comparator
amplifier structure could be considered.

raja.cedt wrote on Jan 6^th, 2012, 2:12pm:


Not sure what the OP is looking for here.
Help when you can right?