Dear friends,
as we know in order to eliminate dependence of threshold voltage on source-bulk potential and thus reduce gata-source voltage of MOS transistors, we can connect source and bulk terminals together. So we need less voltage headroom in comparing with the case when all NMOS bulk terminals are on GND and PMOS ones - on VDD.
I wondering if there are any limitations or negative consequences of doing that? May be there are some applications where it important to keep bulk potentials on supply rails as i wrote above ?
Thanks in advance.

when you do that you are now in a situation where you are driving the capacitance of the well to substrate region.

that capacitance can be very significant and is not in most transistor models, leading to simulation errors.

you need to define the area of your well, that the FET is in, and then approximate that capacitance in your model

Pashtet wrote on Dec 4^th, 2011, 1:46am:

I'm not sure what sriram was talking about, but I agree with Loose Electron. However, I'm sure he'd agree that the extra capacitance isn't a "serious" enough reason to generally avoid doing it - you just need to make sure you model it and weigh the costs against the advantages because the extra capacitance may (not always) cause more issues than is solved.

Another more practical issue in my experience has been the extra area required. The device needs to be in its own well and the well-to-well spacing is relatively large. This can wind up wasting a lot of space so you have to weigh that (and the capacitance) against the performance improvement.

rg

RobG wrote on Dec 4^th, 2011, 8:26am:


Its tough to generalize this one, you need to define the well geometry, determine the capacitance of walls and bottom, and then put it into your model.

Driving that well capacitiance can be significant. Some work I did on an RF PA showed some very extreme differences w/wo the capacitiance. At the end of the day, I talked them into tied well to +V and the big I=Cdv/dt currents got eliminated.

Another example in which it results convenient to connect body to source is in stacked diode connected devices: sometimes the overall voltage drop might be higher than body-drain breakdown and thus having bulk connected to source in each device puts drain-bulk diodes in series, thus larger breakdown characteristics.

Tosei