mjun0mjun
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Dear all, I want to simulate the clock jitter using ADE's pss and pnoise. The simple test schematic is shown in schematic.JPG. And pps and pnoise options are shown in the next two figures, pss.JPG and pnoise.JPG. The pnoise output graph is shown in the last figure, pnoise_simresult.JPG. The problem is that, I don't know the meaning of the pnoise output graph. I expected it would show me some explicit information about jitter. Now I don't know how to calculate the clock jitter from the pnoise output graph. And even is the pnoise output graph right?
Thank you~~ majun
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