hi all,

Here is below my attached schematic of the 4-quad multiplier using translinear principle in subthreshold operation.



The above two oval marked are the Iin1=3nA , Iin2=3nA ,Vdd=0.4V , Ibias in the left of fig is Ibias=3nA , Vbias (below the FGMOS transistors) has the value Vbias=0.4V . input capacitors in the FGMOS are 150fF each at the input terminals (gate) of the PMOS .All MOS are of the same size.

I am doing the DC analysis(parametric) of the above circuit. for Iin1=-3nA to 3nA. And Iin2=-3nA to 3nA with 1nA steps. I expect to get the waveform(ignore the values of Iin1 and 2 in this image) as below.



But i am getting constant 3nA for all values of Iin3 .



Please correct my circuit where its going wrong and suggest me the answer.

Thanks .

Are you sure that sources of all transistors are connected to ground? In this case, you don't have more than 2 transistors in any translinear loop in the circuit...It's not gonna work as a multiplier.

Vladislav D wrote on Dec 7^th, 2011, 10:04am:



Hi Vladislav Sir,

Thanks for your reply,

Ya i have checked the ckt and all the nmos (middle line of 7 nmos FGMOS transistors)sources are connected to the ground and pmos(upper line of transistors) sources are connected to the vdd.

Upper transistors acts as current mirrors, middle line act as for multiplication and the lower two pmos acts as again current mirrors.

Further middle transistors count from left M1 ,M2 ....M7.

Here M2,M4,M5,M6 are the core elements, and M1,M3, M7 duplicate the currents of M2.M4 M6 respectively forming translinear loop.
IMi is the current tru Mi transistor where i=1 to 7
IM2 = IM1= Ib
IM4 = IM3 = Iin1+Ib
IM5 = (IM4 X IM6)/IM2  = (Iin 1 + Ib)(Iin2 + Ib)/Ib

IM6 = IM7 = Iin2 + Ib

If Iin1,Iin2 , Ib then outputs are

Iout1=IM1 + IM5
Iout2= IM3 +IM7

I hope i clarified my question now..

Hope now u r in better position to correct my ckt where its going wrong.

Thanks in advance.

I can't make sense of the circuit. Why do the NMOS devices in the translinear portion have two gates? and are you sure they are hooked up properly?

loose-electron wrote on Dec 8^th, 2011, 8:09am:


Dear Loose-electron Sir/Lady,

In gpdk180 the Vth=0.45V (approx) so,according to you what cuurents i should use..
For subthreshold Vds>4Vth,Vb=0...But i dont have idea about the currents...So please suggest me what currents i should use for my circuit so as to work?

Any if you have any idea about how to know the error tolerance setting of the simulator; you  are welcome.
I am using CADENCE 6.1.4.500 and virtuoso,ADE L/XL. for the spectre simulations.
Thanks a lot ,

Muffassir

Jerry or Loos-electrons is fine...

:)

Plot a set of bais curves for your transistors, and show us for the voltages and currents where you are on those bias curves.

See:
http://www.electronics-tutorials.ws/transistor/tran11.gif

Vladislav D wrote on Dec 7^th, 2011, 10:04am:


OK, I lied and looked at the spaghetti circuit anyway.

Vladislav is absolutely right in my opinion. All of the NMOS transistor sources are connected to VSS so it is nothing more than a current mirror at best. I say at best because a proper current mirror output should have some dependance on its input, but without a proper definition of what those two gates are who knows what the circuit actually is. (How can you have a connection to a "floating gate anyway?).

A translinear loop needs to have a loop where Vgs1+Vgs2 = Vgs3 + Vgs4, which you do by connecting the source of two devices to the gates of two other devices. Then the gates of the top-most devices are also connected together creating a 4 transistor loop. https://www.google.com/search?q=translinear+circuit&oe=utf-8&rls=org.mozilla:en-...
This circuit has no such loop so it is nothing more than a current mirror.

grrrrrr... you are sweeping I3, but I don't see where I3 is even used in the circuit.