Hi, I have followed the tutorial on PLL from Designer's guide. I did the example of the tutorial and correlated the results for the output phase noise with matlab (by looking at the overall closed loop transfer function, the cutoff frequency corresponded as well as the gain etc). However, when I synthesize a closed loop tf with higher cutoff, in the MHz range, my results do not correlate anymore, I have a shift in my peak frequency (it is lower).

I went back and fort to check if I set my VCO gain, charge pump current, and the transfer function are set correctly, but I do not see any issues. I have implemented the transfer function using the lapace_nd command (and verified it works by implementing the example in the tutorial, actually replacing the filter with the transfer function).

I have decrease reltol,  vabstol, but I still have that issue.

PS: My reference frequency is 100MHz.

Thank you
George

Please read Ken'sGet your question answered
http://www.designers-guide.org/Forum/YaBB.pl?num=1252743617.

I suggest you put the question in more detail. Perhaps some plots, either the block diagram or the phase noise plot is helpful.

Thank you for your replies. I will reformulate the problem in more details.
So all that I am doing is using Ken's tutorial on "Modeling Jitter in PLL-based Frequency Synthesizers" in order to further test some high level PLL implementations.  I have synthesize the phase response in Matlab of the PLL as  a 3rd order butterworth filter. Using some given parameters for the VCO such as :

Fmin = 29e9;
Fmax = 41e9;
Vmin = 0;
Vmax = 1;

And the current for the phase frequency charge pump set to 200uA, as well as the reference set to 100 MHz, I found out the PLL filter should be:

 5.053e16 s + 7.938e22
--------------------------------------
0.7639 s^3 + 1.2e07 s^2 + 9.048e13 s

The phase noise of the PLL is given to be -101.8 dBc/Hz @ 1.186MHz [this is actually from a schematic extraction, it will be much worse after layout  :| ], for a frequency of 32GHz. The jitter that corresponds to this phase noise is  1.6841fs.

This is where the trouble comes. When I simulate the VCO alone with a fixed DC input voltage, the phase noise plot I get does not give me the -101.8dBc/Hz @ 1.186MHz,  [I have included the divider and the resolution bandwidth as well in the phase noise total dBc/Hz computation. In order to get my -101.9dBc/Hz I had to increase the jitter std up to 10fs.  Furthermore, when I connect the PLL blcoks together in a schematic file and only add jitter (1ps) at the main oscillator Reference, the plot I get for the phase noise at the output of the PLL does not correspond to the closed loop transfer function I have generated with matlab ie: the response is shifted down in frequency (I have attached a picture).

Below is the verilog-A for the transfer function:

module Filter_Tf(in,out);
inout in;
output out;

electrical in,out;

real num_hs[0:3];
real den_hs[0:3];

analog begin
       @(initial_step)begin
       num_hs[0] = 7.937606830156752e+22;
       num_hs[1] = 5.053237453357751e+16;
       num_hs[2] = 0;
       num_hs[3] = 0;

       den_hs[0] = 0;
       den_hs[1] = 9.047786842338605e+13;
       den_hs[2] = 1.200000000000000e+07;
       den_hs[3] = 0.763943726841098;
       end

       V(out)<+ laplace_nd(I(in),num_hs,den_hs);
end
endmodule


PS: I designed a delta-Sigma as well but did not include it in the schematic yet until I get rid of this issue. If I scale all my frequencies down, I am not sure I can assume the problem to be linear when I will include my delta sigma in the feedback loop...w.r.t how the phase noise at the output of the VCO will affect the delta sigma ( and I would like to synthesize the delta sigma and do a post layout simulation).

Thank you

I have assumed a phase noise for the reference oscillator of -100dbc @ 100KHz offset.  

I think I will go with  Marq Kole's suggestion, and scale the frequency down, the filter as well, the delays and rise/fall times etc, but retain the phase noise, so the jitter will be higher, in this sense the relationship for the delta sigma divider in the loop should be linear.

Thank you
George