GMachine
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Thank you for your replies. I will reformulate the problem in more details. So all that I am doing is using Ken's tutorial on "Modeling Jitter in PLL-based Frequency Synthesizers" in order to further test some high level PLL implementations. I have synthesize the phase response in Matlab of the PLL as a 3rd order butterworth filter. Using some given parameters for the VCO such as :
Fmin = 29e9; Fmax = 41e9; Vmin = 0; Vmax = 1;
And the current for the phase frequency charge pump set to 200uA, as well as the reference set to 100 MHz, I found out the PLL filter should be:
5.053e16 s + 7.938e22 -------------------------------------- 0.7639 s^3 + 1.2e07 s^2 + 9.048e13 s
The phase noise of the PLL is given to be -101.8 dBc/Hz @ 1.186MHz [this is actually from a schematic extraction, it will be much worse after layout :| ], for a frequency of 32GHz. The jitter that corresponds to this phase noise is 1.6841fs.
This is where the trouble comes. When I simulate the VCO alone with a fixed DC input voltage, the phase noise plot I get does not give me the -101.8dBc/Hz @ 1.186MHz, [I have included the divider and the resolution bandwidth as well in the phase noise total dBc/Hz computation. In order to get my -101.9dBc/Hz I had to increase the jitter std up to 10fs. Furthermore, when I connect the PLL blcoks together in a schematic file and only add jitter (1ps) at the main oscillator Reference, the plot I get for the phase noise at the output of the PLL does not correspond to the closed loop transfer function I have generated with matlab ie: the response is shifted down in frequency (I have attached a picture).
Below is the verilog-A for the transfer function:
module Filter_Tf(in,out); inout in; output out;
electrical in,out;
real num_hs[0:3]; real den_hs[0:3];
analog begin @(initial_step)begin num_hs[0] = 7.937606830156752e+22; num_hs[1] = 5.053237453357751e+16; num_hs[2] = 0; num_hs[3] = 0;
den_hs[0] = 0; den_hs[1] = 9.047786842338605e+13; den_hs[2] = 1.200000000000000e+07; den_hs[3] = 0.763943726841098; end
V(out)<+ laplace_nd(I(in),num_hs,den_hs); end endmodule
PS: I designed a delta-Sigma as well but did not include it in the schematic yet until I get rid of this issue. If I scale all my frequencies down, I am not sure I can assume the problem to be linear when I will include my delta sigma in the feedback loop...w.r.t how the phase noise at the output of the VCO will affect the delta sigma ( and I would like to synthesize the delta sigma and do a post layout simulation).
Thank you
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