Hello,

I have to design a CMOS-LNA at 868 MHz. The Problem is, that it should be a low power LNA, so it is preferable to realize matching with passive components. The input impedances of the used MOS transistors are very capacitive, so I have to use inductances more than 20 nH which can't be realized integrated. Another idea was to use an common gate stage for inputmatching, but there is the drawback that you have to realize also an inductor off chip. Has somebody another idea how to match the input without consuming further current ? Thanks for response.

Hi,


I guess you need to try and lower your input Q by either placing a cap across Cgs, or increasing the source inductance. Inductor Q is low at 868-MHz, so it will be difficult to match to high Q.

Bear in mind that in a common-source type amplifier, you never actually match to the device since the Q is too high at low-GHz frequencies. You need to synthesize a resistance to match to. Of course the most common-method to synthesize an input resistance is using inductive degeneration since it gives the best NF. You should synthesize a resistance that you can conveniently match to. i.e. design the input Q so that you can match to it. The tradeoff is that the lower the input Q you design, the lower your matching network's voltage gain.

Another option is to design the common-gate with higher than 50-ohm input impedance. Then use the source inductor and input capacitor as a step-up network. This way you can lower your LNA's power consumption. The challenge will be to design a high-Q source inductor.

One more possibility is to lower the self-resonant frequency of your inductor by placing a capacitor across the terminals. This will make it more inductive, but the drawback is first you need to model your inductor well, and second you will increase the order of your matching network.

Sorry if my response was too elementary. Maybe you could describe your problem more elaborately...


cheers,
Aaron