Hi,

The system runs at +3.3V.

However the input may +3.3V digitial signal or it may also be +5V signal.

That is the system should tolerate +5V inputs.

I need to implement ESD protection for such a scenario.

Can someone please suggest a solution? or direct me to any papers or links?

Thanks.

Since your input is greater than the power supply you can't have that diode to 3.3V unless...
1) you put a series resistance before the ESD to limit the current (probably not desirable since you will be injecting current into the substrate every time the vdd diode turns on).
2) you use a voltage divider before the ESD to attenuate the input to 3.3V max. This is probably the easiest if you can tolerate a resistive input. You could then AC couple to an inverter biased mid-rail that will gain the signal back up to rail-to-rail levels when the input is 3.3V.
3) you put a resistor from input to a virtual ground. This would look like an inverting opamp circuit, except you would have a really simple opamp. Again, this would require that the input drive a resistive load.

Otherwise you will have to use some snapback device or an AC coupled clamp or devices based on a vbe multiplier, etc. Sorry, I let someone else do the esd and I can't find any schematics on the web to illustrate what I'm talking about!

Analog or digital input?  How fast?

Digital is easy.  You just put a five volt nmos transistor drain on the pad with the gate tied to the 3.3V rail.  Use a resistor to ground on the source. Connect a buffer from the source as your input stage  Watch out for iddq current though because the input buffer won't go to the rail.

Analog you should do the resistive divider as suggested.

Putting diodes in series or large resistors in series are not good solutions for esd  You will need some kind 5V SCR or similar Snapback structure.

For the digital input device can't you still do the same type of source follower trick with a 3.3V device?  The gate is tied to 3.3V so the source is limited to 3.3-Vt.  The drain max is 5V so the max drain to source will be 5-3.3-Vt.

For the protection structure:

A typical structure will be a cascode stack of two 3.3V nmos transistors drawn to esd rules.  Of course I am assuming you have 3.3V oxide...

Often the gates are biased during esd by zeners, capacitors, or some combination.  Try a google search for 5V tolerant ZCGNMOS and see what comes up.

These 5V tolerant structures are tricky to get right and often require a couple spins of silicon to get working. The primary issue is the turn on speed and resulting voltage overshoot.

A lot of 1.8V and below ESD uses a cascade of
ESD structures with resistors in between.

All of a sudden that 0.6Vpn starts to look a bit too big.

For this --
Level shifting the 5V signal down using resistive voltage division
is a common thing that gets used.

Simple and functional, no gate oxides to protect until you
are under the lower voltage rail.

Added bonus, NWell resistors looking like a diode to substrate
in the negative ESD events.

Unless we are talking really fast transisents, the LPF due to the
resistance usually is not a problem.

Snapback devices are generally not documented in foundry
provided model sets, so it depends on your relationship with the foundry.

I work at the foundry so I take the snapback for granted .

I mostly have experience for older technos so it's interesting to hear about protection schemes in newer ones.

Our caps usually have a thicker oxide and breakdown above the esd clamps...

One thing is for sure:  it's always better to make things as simple as possible!

Good luck.