Hi Guys,

Happy new year to all!

I was trying to improve freq response of an LDO using lead-lag compensation technique. Its a classical LDO from architecture point of view. That is having an error amp, followed by a PMOS pass device. It uses a 1uF cap to create the dominant pole. Problem is the error amp (EA) has 2 poles, and the compensation isn't great. I wanted to try out some text book external compensation methods (rather than internal miller compensation), that is putting R and C around the EA to add zeros and poles to improve the freq response. Couldn't get that working! And after some thought I find one major difference between what I am doing and what the books suggest is that my EA is an OTA really, with high output impedance, rather than an ideal OPAMP with small output impedance. This confused me so much that I am posing some basic questions.

1. Don't you think there is a fundamental difference in applying an external compensation (i.e. putting R and C) on an OTA and an OPAMP? I cannot do it in the same way as it shows in text books for example using an OTA?

2. More basic question: if I consider an inverting amplifier with R1, R2 connected in standard way around an OTA, rather than an OPAMP, wont it affect the open-loop gain of the OTA itself and hence affecting the transfer function? What I understand the feedback resistor R2 (between output and the negative terminal) will start loading the output stage of the OTA and hence affect its open loop gain?

Pls. let me know what do you think.

Rajdeep

hello,
1. dont be confused with terms called OTA and opamp. You have to see whether you have drive high impedance or low impedance, in case of high impedance you don't need to care about current required by the amplifier, so OTA (again OTA means amplifier with high impedance) can drive, in case if you want to drive low impedance load you have to use an buffer in between amplifier and load (this is called opamp).

2. You don't need to design op amp (better cal it as amplifier rather op amp), because this amplifier is not driving any low impedance and your o/p is driving the load so it should have low impedance and by default there is shunt feedback hence it can drive (the impedance of an regulator is 1/(A*gm))

3.Regarding inverting amplifier yes it will effect the gain of the last stage, and many cases this is the reason why people go for two stage at least (again this is called opamp rather OTA)

3. Coming to your regulator design you have designed 2 stage op amp for error amplifier, due to the fact that you mentioned that you have 2 poles in the error amplifier and one is the o/p pole. so better use single stage opamp in the first stage (of course it depends on the how much dc psrr you need), and try compensate through pole zero compensation.

Sorry for the big reply. Try to post the bode plot if posb.

Thanks,
raj.

Hi Raja,

Thanks for the reply! Yes I was also thinking of explaining what I mean by OTA and OPAMP really before asking the questions. Lets use amp_hi as amplifier with high o/p impedance, and amp_lo for an amp with low o/p impedance.

In (3) you agree with the loading point but mention that one should go for 2-stage. But then the second stage has to be a buffer I guess to ensure low o/p impedance? [As you mentioned in point (1)].

So in summary I really cannot add poles-zeros by adding R,Cs across an amp_hi. I need to use an amp_lo?  For example if you can look at this link: http://www.intersil.com/data/an/an9415.pdf I just googled and found this. If you look at Fig 26 for example, that amplifier has to be an amp_lo, right?

Sorry if I am asking you the same thing again!

About the regulator design, the LDO works in silicon! But strangely it's phase margin is very poor, but still works!! Nevertheless, I was trying to improve it by employing some lead-lag network without modifying the error amp itself, when I observed this fundamental issue.

Thanks,
Rajdeep

Hi Raja,

In a standard negative feedback network we add a feedback network to achieve negative feedback so that the closed loop gain is determined by the feedback network only. Now that feedback network I guess should not load the original forward gain circuit. For example, in that same document Figure 1, β network should not load A network. If β starts to load A then A may not remain significantly high and hence will make the whole thing....well very complicated! Thats why I think a feedback network like in Fig 26 should not load the amplifier whose main task is to provide a large gain. Thats why I think it should be an amp_lo.

cheers!
Rajdeep

Hi Raja,

I agree to your point of reduction of o/p impedance due to negative feedback. I guess what you have been trying to tell me is that one doesn't have to reduce the o/p impedance of the amplifier as the negative feedback will do that anyway. Also, the 1st stage of the amplifier should have enough gain, such that the reduction of the second stage gain due to loading of the feedback network should still provide enough overall gain in the feedforward path. I hope I got it correct this time?

But I think the nice transfer functions derived for lead-lag compensator assumes very easily rout of the amplifier small! A higher rout of the amplifier complicates the whole situation as the feedback network modifies the original open-loop bode plot of the amplifier. Will try to experiment this with 2 different amplifiers and see...

Thanks for the replies guys!
Rajdeep

Hi,

I have a curious thing happening now after I have 'improved' the phase margin of the overall loop. But it makes the transient response worse and actually shows oscillation. I am attaching the Bode plot and  transient response, and also a simple block diagram of the ldo. Do you think I am missing something from the Bode plot? The phase margin, gain margin appear to be all right but the bump at the phase plot could indicate something. Could anyone help me out here understanding what could be going wrong?

To do the ac analysis I have simply cut the vfb node and added an ac signal there and observed the loop gain from vfb to output i.e. drain of PMOS. I havent shown the compensation I have added. This done at 10mA load current (not shown). To do the transient I enable at the LDO with a 10mA load current with the vref input already being settled.


Thanks,
Rajdeep

hello,
i am attaching one one bode corresponding to similar kind of regulator. At least before UGB response is monotonic.

Thanks,
Raj.

hello,
you should  have monotonic for both phase and magnitude. Let us say you have monotonic gain fall but if you have some non-monotonicity in phase, means there is chance of encircling -1,0 point.

.PZ gives real and imaginary parts of the pole so you can find location, but the disadvantage of this method is it gives so many poles and zero's at high frequency and many doublets, so you have to search a lot for the dominate one.

Thanks,
raj.