Hello Everyone,

This is for those members who have done both simulation and measurement from chip.

I have a question regarding output resistance of certain building blocks like opamps, OTA's etc.. Normally the output resistance is constant for the block from DC till certain frequency after which the parasitic capacitances in the transistor make the output resistance to fall down at higher frequencies.

Based on your experiences, can anyone tell me how close the simulated and measured values are for a advanced technology node such as UMC or TSMC 90nm/130nm. I understand that mismatch and other effects will be present. However I am only looking for a rough value or maximum percentage difference between the two.

I have not done a tapeout myself so I dont know how much I can trust the values given by the simulation.

Thanks for your help.

Hi raj,

Lets consider the TSMC or UMC 90 nm process. Based on this assumption if I design an OTA with a certain output impedence and send it to tapeout and finally measure it, than my question is how much of a variation can I expect between the simulated and measured output impedence. 5% 10%, 20% . I know that no exact value can be given but I would like to know none the less whats the maximum variation I can expect.

As you said this is also closely related to how good the models are. I have no clue about how the models are compared to actual measured values which is why I ask here if anyone who has used such a process can enlighten me about the maximum variation I can expect.

Thanks again

hacksgen wrote on Jan 9^th, 2012, 1:45am:


Hi hacksgen,

If your building blocks are gonna be used in -ve fbk configuration (sampling voltage) then this statement is not true: as loop gain decreases, above dominant pole freq, the output impedance will start increasing (from a very low value at low frequencies). This impedance will increase until closed loop -3dB freq is reached, at which it will remain constant.
Finally at very high frequency the parasitics you are asking about is when they will start playing a role.

Best
Tosei

Variance between simulation and silicon.

Start with the premise that the weak-strong model corners
already have a lot of variance.

Will you be inside those limits if you include
everything in the model?

Generally yes. Give the below a read, it should help
you set up your model properly.

http://electronicdesign.com/article/eda/simulation-vs-silicon-avoid-costly-mista...

Here's the original PDF (easier to read):
effectiveelectrons.com/whitepapers/simulationvssilicon.pdf


That might be useful background.