raja.cedt wrote on Jan 12th, 2012, 1:20am:hello,
for a simple CS amplifier, how change in vdd will lead to BW enhancement, because for given bias current the BW depends on the load cap and Vov of the input device, so try to it wont impact BW much.
Thanks,
Raj.
Thanks for the reply, Raj
The point is I don't use any load cap there.
Therefore, only the fet's parasitic capacitance will work.
My adviser keeps telling me that with Vdd increasing , the BW will definitely go up but my simulation results are always opposite.
I try to maintain the gain to be almost the same and make the transistor size smaller under each Vdd with a give bias current.
Theoretically, BW ∝ Id/Cl, here Id is constant so if I decrease Cl, the BW should go up. In my case, however, it always goes down.
I am very confusing of that.
Thanks
Hai