Hi, guys

Recently, I have worked on some simulations about the CS amp design with Avago A10 process.

The structure is fairly fundamental. A PMOS transistor on top works as an active load and a NMOS transistor at the bottom will provide the gm.

The requirements are as below:
The input and output DC voltage will be Vdd/2 strictly and the Vdd will vary from 2V to 5V for 10 steps.
The bias current will vary from 2uA to 20uA with 10 steps. Under each bias current, the voltage will change from 2V to 5V.

It will generate a bunch of simulations.

My question is, under Id = 2uA for example, when I vary Vdd from 2V to 5V for each step, is that possible to make the bandwidth still go up?

I have tried many ways but the BW always goes down.


Thanks and regards
Hai

raja.cedt wrote on Jan 12^th, 2012, 1:20am:


Thanks for the reply, Raj
The point is I don't use any load cap there.
Therefore, only the fet's parasitic capacitance will work.
My adviser keeps telling me that with Vdd increasing , the BW will definitely go up but my simulation results are always opposite.

I try to maintain the gain to be almost the same and make the transistor size smaller under each Vdd with a give bias current.

Theoretically, BW ∝ Id/Cl, here Id is constant so if I decrease Cl, the BW should go up. In my case, however, it always goes down.

I am very confusing of that.

Thanks
Hai

hello hai,
i don't know how Vdd changes your BW. Any how Please post the schematic. Seems you are beginner in analog so i would suggest you to refer Micro electronics book by razaavi or analog design essentials by Willy sansen.

Thanks,
Raj.

Did you checked the output impedance? If vds increases the gds will decrease, i.e. the load resistance increases. This can decrease the BW at higher supply voltages.
Could this be the case?