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Hi An inverter with minimum channel length(L=65nm) in tsmc 65nm LP process is designed. The recommended supply voltage of the inverter from tsmc is 1.2V. (1) If the inverter is used as a static inverter, could the supply voltage vdd be more than 2.5V? (2) IF the inverter is used as an clk buffer (Fclk=80MHz0), could the supply voltage vdd be more than 2.5V?
I have reversed an third party chip. In the chip, there is some inverters designed with minimum length(L=65nm), but the supply voltage of these inverter should be more than 2.5V by circuit analysis. Can this be reasonable?
Thanks .
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