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nus_lin

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problem with small capacitor in layout
Feb 23^rd, 2012, 8:47pm

dear guys,

i have a similar problem in using a small capacitor in layout. The minimum MOM capacitor offered by the design kit is around 15ˣ15um2,which is much larger than what we want. Therefore, if my unit capacitor is smaller than that value, I am not able to pass the LVS check, and can not run the post-layout simulation either.

can anyone advise me how to get this done?

thank you in advance.

regards,
HE LIN

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yvkrishna

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Re: problem with small capacitor in layout
Reply #1 - Feb 23^rd, 2012, 11:44pm

hi HE LIN,

I understand that the minimum cap value realizable as per layout guidelines is �higher that what you need in the design. �

What is the order of cap value you are looking for ? if it too small the adjacent parasitic cap can simply dominate it.

And you can use caps in series , or a combination of series and parallel caps to get to the value you wanted.

Regards,
yvkrishna

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raja.cedt

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Re: problem with small capacitor in layout
Reply #2 - Feb 24^th, 2012, 2:30am

Why don't you make MIM caps by yourself in top metal?? It offers less capacitance based on your requirements. people go for MOM cap only if they need big capacitors but in your case it is different. If you want to go with PDk caps as vamsi suggested go with series combinations of big capacitors, in fact this is a good option if you need less mismatch as well..

Enjoy

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: problem with small capacitor in layout Reply #3 - Feb 24^th, 2012, 2:13pm what value of C are you looking for? what is the value of parasitic C presented to substrate by the metal interconnect at the node of interest? if those two values are anywhere near each other you need to redesign your circuit to use a larger C.
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nus_lin

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Re: problem with small capacitor in layout
Reply #4 - Feb 24^th, 2012, 7:11pm

thank you, vamshikrishna, raja.cedt, and loose-electron

actually i am already using c-2c architecture to reduce the effective capacitance.

the process i am using is 65nm, where mim cap is impossible. the only choice is mom cap. the unit capacitor i am trying to implement is 8fF, which should be much less than parasitics.

the ninimum mom cap in design kit uses 25 fingers, and is 32fF. so i am quite sure, if there is a way to adjust the minimum finger requirement so that i can use 9fingers, then things will become quite easy.

problem is how?

yvkrishna wrote on Feb 23^rd, 2012, 11:44pm:

hi HE LIN,

I understand that the minimum cap value realizable as per layout guidelines is �higher that what you need in the design. �

What is the order of cap value you are looking for ? if it too small the adjacent parasitic cap can simply dominate it.

And you can use caps in series , or a combination of series and parallel caps to get to the value you wanted.

Regards,
yvkrishna

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RobG

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Bozeman, MT

Re: problem with small capacitor in layout
Reply #5 - Feb 25^th, 2012, 8:50am

You can build a cap with nine fingers if you like, but you will have to waive the DRC rule violation which is a matter of company policy, not physics (bear in mind the 9 finger cap isn't going to be as accurate as the 25 fF cap - watch parasitics). You need to be talking with your supervisor and process guys about this to see if they will let you build a cap that small since it will violate the rules.

At ISSCC this year someone had a 0.6 fF cap in their design.

nus_lin wrote on Feb 24^th, 2012, 7:11pm:

thank you, vamshikrishna, raja.cedt, and loose-electron

actually i am already using c-2c architecture to reduce the effective capacitance.

the process i am using is 65nm, where mim cap is impossible. the only choice is mom cap. the unit capacitor i am trying to implement is 8fF, which should be much less than parasitics.

the ninimum mom cap in design kit uses 25 fingers, and is 32fF. so i am quite sure, if there is a way to adjust the minimum finger requirement so that i can use 9fingers, then things will become quite easy.

problem is how?

yvkrishna wrote on Feb 23^rd, 2012, 11:44pm:

hi HE LIN,

I understand that the minimum cap value realizable as per layout guidelines is �higher that what you need in the design. �

What is the order of cap value you are looking for ? if it too small the adjacent parasitic cap can simply dominate it.

And you can use caps in series , or a combination of series and parallel caps to get to the value you wanted.

Regards,
yvkrishna

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loose-electron

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Re: problem with small capacitor in layout
Reply #6 - Feb 25^th, 2012, 12:46pm

"At ISSCC this year someone had a 0.6 fF cap in their design."

Yeah, and I have seen a lot of other stupid stuff in papers and presentations.

Things like that get lost in the process variance, or got added to tweak
a simulation, and don't have a lot to do with what happens on silicon.

I remember a S&H circuit where it was really small hold
capacitor, and when I asked the designer about the input capacitance
of the transistor connected to it, they drew a blank.

Turns out the input capacitiance of the next transistor was
about 50X bigger than the "hold" capacitor.

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loose-electron

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Re: problem with small capacitor in layout
Reply #7 - Feb 25^th, 2012, 12:49pm

nus_lin wrote on Feb 24^th, 2012, 7:11pm:

i am trying to implement is 8fF, which should be much less than parasitics.

a controlling capacitor in a circuit should be much larger than the parasitics
at the node. Not smaller.

You want your explicitly defined device to be the primary control
not the parasitics.

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nus_lin

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Re: problem with small capacitor in layout
Reply #8 - Feb 27^th, 2012, 1:06am

sorry, by less i actually mean bigger.

loose-electron wrote on Feb 25^th, 2012, 12:49pm:

nus_lin wrote on Feb 24^th, 2012, 7:11pm:

i am trying to implement is 8fF, which should be much less than parasitics.

a controlling capacitor in a circuit should be much larger than the parasitics
at the node. Not smaller.

You want your explicitly defined device to be the primary control
not the parasitics.

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Lex Senior Member Offline Posts: 201 Eindhoven, Holland	Re: problem with small capacitor in layout Reply #9 - Feb 27^th, 2012, 4:39am You could try widening the spacings of the MOM and then verify the capacitance with the extraction tool. Since at that point you are making your own device, you are then dependent on the accuracy of your parasitic extractor (not without risk).
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RobG

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Re: problem with small capacitor in layout
Reply #10 - Feb 27^th, 2012, 5:56am

loose-electron wrote on Feb 25^th, 2012, 12:46pm:

"At ISSCC this year someone had a 0.6 fF cap in their design."

Yeah, and I have seen a lot of other stupid stuff in papers and presentations.

Things like that get lost in the process variance, or got added to tweak
a simulation, and don't have a lot to do with what happens on silicon.

It was in a cap DAC for a SAR. Caps in the few fF range are becoming more common.

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boe

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Re: problem with small capacitor in layout
Reply #11 - Feb 27^th, 2012, 7:04am

Hi,
RobG wrote on Feb 27^th, 2012, 5:56am:

loose-electron wrote on Feb 25^th, 2012, 12:46pm:

"At ISSCC this year someone had a 0.6 fF cap in their design."

Yeah, and I have seen a lot of other stupid stuff in papers and presentations.

Things like that get lost in the process variance, or got added to tweak
a simulation, and don't have a lot to do with what happens on silicon.

It was in a cap DAC for a SAR. Caps in the few fF range are becoming more common.

My tuppence worth: As long as you know what you are doing, fine. Otherwise, a recipe for disaster.
- B O E

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loose-electron

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Re: problem with small capacitor in layout
Reply #12 - Feb 27^th, 2012, 2:24pm

RobG wrote on Feb 27^th, 2012, 5:56am:

loose-electron wrote on Feb 25^th, 2012, 12:46pm:

"At ISSCC this year someone had a 0.6 fF cap in their design."

Yeah, and I have seen a lot of other stupid stuff in papers and presentations.

Things like that get lost in the process variance, or got added to tweak
a simulation, and don't have a lot to do with what happens on silicon.

It was in a cap DAC for a SAR. Caps in the few fF range are becoming more common.

Yeah, and KT/C noise hasn't changed last I checked.

:)

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Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

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Lex Senior Member Offline Posts: 201 Eindhoven, Holland	Re: problem with small capacitor in layout Reply #13 - Feb 28^th, 2012, 3:58am Hahahah =D Good point! Just out of curiosity, could you pass the link to that paper?
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RobG

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Re: problem with small capacitor in layout
Reply #14 - Feb 28^th, 2012, 7:55am

Lex wrote on Feb 28^th, 2012, 3:58am:

Hahahah =D

Good point!

Just out of curiosity, could you pass the link to that paper?

Lex - the paper was 27.8 by Pieter Harpe, but you won't find much information there. However, last year he had a JSSC paper that talked about building a 0.5 fF capacitor with 90nm CMOS. It is here: http://ens.ewi.tudelft.nl/pubs/meijs11jssc.pdf

It seems to have some good information in it.

kT/C noise isn't much of an issue since the signal is sampled onto the entire DAC, not just the LSB cap.

rg

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