thank you, vamshikrishna, raja.cedt, and loose-electron
actually i am already using c-2c architecture to reduce the effective capacitance.
the process i am using is 65nm, where mim cap is impossible. the only choice is mom cap. the unit capacitor i am trying to implement is 8fF, which should be much less than parasitics.
the ninimum mom cap in design kit uses 25 fingers, and is 32fF. so i am quite sure, if there is a way to adjust the minimum finger requirement so that i can use 9fingers, then things will become quite easy.
problem is how?
yvkrishna wrote on Feb 23rd, 2012, 11:44pm:hi HE LIN,
I understand that the minimum cap value realizable as per layout guidelines is higher that what you need in the design.
What is the order of cap value you are looking for ? if it too small the adjacent parasitic cap can simply dominate it.
And you can use caps in series , or a combination of series and parallel caps to get to the value you wanted.
Regards,
yvkrishna