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The Designer's Guide Community Forum › Simulators › AMS Simulators › SpectreVerilog: "reset" signal stays in "stx"
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SpectreVerilog: "reset" signal stays in "stx" (Read 2442 times)
ahhfyz
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SpectreVerilog: "reset" signal stays in "stx"
Feb 24th, 2012, 11:05pm  
Hi, everyone!

I am simulating a mixed signal system using SpectreVerilog. In digital part, there is a "reset" pulse signal, whose width is 100ns. However, it stays in "stx", therefore the digital circuits cannot be reset, and simulation result is no sense.  How could this happen? Thank you!
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boe
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Re: SpectreVerilog: "reset" signal stays in "stx"
Reply #1 - Feb 27th, 2012, 6:37am  
Hi Ahhfyz,
It is difficult to give you a concrete answer with so little information:
Which tool version do you use? Where does the reset come from? What IEs do you use? Do you simulate power-up phase? Waveforms?

- B O E
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