tomaul1 New Member Offline Posts: 1

Need help with Arithmetic & Logic Unit Mar 05th, 2012, 3:51pm   Hello, let's say I have this module: module ALU(      input      carryIn      ,            input      [2:0]      func            ,            input      [31:0]      left, right      ,            output reg            carryOut      ,            output reg      [31:0] out ); always @(left or right or func or carryIn) case (func) 3'b000: {carryOut, out} = left + right + carryIn;     //add 3'b001: {carryOut, out} = left - right – carryIn;      //sub 3'b010: {carryOut, out} = {1'b0, left & right};        //and 3'b011: {carryOut, out} = {1'b0, left | right};        //or 3'b100: {carryOut, out} = {1'b0, left ^ right};        //xor 3'b101: {carryOut, out} = {1'b0, ~left};                //not 3'b110: {carryOut, out} = {1'b0, left};                      //left 3'b111: {carryOut, out} = {1'b0, right >> 1} ;       //shr endcase endmodule and the following module that incorporates the ALU: module alu_acc( output reg [31:0] acc_reg ,                         input [31:0] in ,                         input [2:0] func ,                         input cin ,                         output cout ,                         input clock );                 wire [31:0] out; ALU alu(.out (out) ,            .carryOut (cout) ,            .carryIn (cin) ,            .left (in) ,            .right (acc_reg) ,            .func (func) ); always @(posedge clock) acc_reg = out; endmodule At every positive edge of the clock, we apply {func,cin,in}={..}, so if we apply: {func, in, cin} = {3'b000, 31'b101, 1'bx} // acc_reg = 31'b101 {func, in, cin} = {3'b010, 31'b010, 1'b0} // acc_reg = acc_reg + 31'b10 + 0 {func, in, cin} = {3'b011, 31'b011, 1'b1} // acc_reg = acc_reg - 31'b11 - 1 then we get acc_reg=31'b011. I am asked to modify the ALU module in order to make the same operations to a string of numbers, in which the negative numbers are represented in 2's complement. I can't figure out what to modify, where to modify or anything else... Please help me with this, I am just starting to learn verilog and Digital Integrated Circuits, so I am limited to ideas for solving this. Thank you very much!

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