i have designed single ended low noise amplifier  with cascode source degeneration configuration to be operating at 2.14GHz and i m getting
S11 = -17.85dB
S21 = 12dB
both tuned at 2.15GHz
also input referred noise around 6.224E-18 V(sqr)/ Hz
but i m not able to design output impedance matching network so that S22 to be tuned at 2.14GHz
I tried pi matching network but that dropped my gain to 2dB
pls help
thanks in advance

As Jerry said, we need to see your topology before good suggestions can be provided.

If your gain is dropping because of matching then the problem is that you need to understand what to do to meet your gain requirement with matching. You need to find out what the output impedance is of your circuit and understand that matching will tune out the reactive part while loading the transistor with 1/2 the real part of the output impedance (conjugate match). The gain from your matched output to the load will be the square root of the impedance ratio sqrt(Rload/Rtransistor). If your load impedance is much lower than the output impedance of the transistor then the match will step down the voltage from the transistor to the load resistor. If the load is higher impedance than the transistor then the match will step up the voltage.

The gain with matching is something you can calculate and design for if you know what the output impedance of your amplifier is (before matching).

The other important point is topology and isolation to the input. If you have a common source (or emitter) amp without a cascode then the input and output networks are somewhat connected through the drain to source (or collector to base) capacitance. This output to input coupling makes it much more difficult to isolate the output and input matching circuits. However, if the circuit is a cascode structure for the input then there is high isolation between output and input making it a little easier to deal with matching and gain requirements for the design.

So tell us more about the topology.

thanks a lot  RFICDUDE i need some explain how
The gain from  matched output to the load is related to  the square root of the impedance ratio sqrt(Rload/Rtransistor).

-If u need a narrow-band matching just put parallel RLC in the collector and remove that pi-crap from the output. With R u can vary the BW in expense of gain
-make C tunable to overcome process variation
-decouple the output port from the circuit

Purpose of R1 & M2?

Why is there a signal generator on the output of the device?
(i think its a test tool, but please verify)

At first look, the DC op point does not seem to make sense,
could you please provide the node voltages and currents
at the DC operating point?

Set the voltage = 0 monitor the current in the voltage source.

It exists in the schematic,
but is meaningless in the final circuit on silicon.

As Vladislav first pointed out, the gate bias circuit is not valid.

The input bias appears to be a current mirror reference diode, but the gate and drain are not tied together. The gate voltage of the input device appears to be indeterminate for the circuit shown.

Beyond the reference device issue, the current mirror reference device has a width=6u and the amplifier has width=0.24u resulting in a step down of 0.24/6=0.04 in current from the reference device to the amplifier. Typically we want a step up in current arising from the reference device width being smaller than the amplifier device it is biasing.

schematinc with dc node voltages