Designer’s Guide Community

Vladislav D

Community Member

Offline

Posts: 76
The Netherlands

Re: need help
Reply #15 - Mar 19^th, 2012, 1:50pm

First of all, please, draw a schematic clearly, if you want people help you. Electronics does not like rush.

Use the M parameter for transistors and inductors and make the connection between components reasonably short. Voltages in the schematic are hardly readable. Currents are important as well!

At this step of the design, I'd suggest to use ideal inductors, capacitors and the ideal current source to bias M2.

You must place a capacitor between the output port and the output of the amplifier in order to bias the transistors properly

Matching network at the input is too complex. It is possible to match input with a series inductor at the gate and some inductance at the source. You can do some research. The methodology to do this exist. For example, you can read http://www.amazon.com/Co-Design-Integrated-Receivers-International-Engineering/d...

Back to top

IP Logged

varun patial

Junior Member

Offline

Posts: 18

Re: need help
Reply #16 - Mar 21^st, 2012, 10:47pm

thanks a lot Vladislav D
i tried putting capacitance before the output port and that proved to be effective in decreasing my power . I have following query
1)how to decide where to use ideal passive components and where to use rf passive components in the schematic.
2) how to optimize the value of inductance i m attaching two files
i m confused how to set diameter,width and no. of turns.
for example with one file attached i can use single inductor of value 14.27nH
and with other one i can use two inductors of value around 7nH in series with varying values

Back to top

1_010.jpg

IP Logged

varun patial Junior Member Offline Posts: 18	Re: need help Reply #17 - Mar 21^st, 2012, 10:48pm 2nf file
Back to top	2_005.jpg IP Logged

Vladislav D

Community Member

Offline

Posts: 76
The Netherlands

Re: need help
Reply #18 - Mar 22^nd, 2012, 4:39pm

Diameter, width, number of turns this is a physical design. At your design step this only distractions, as well as various non-ideal effects related to the physical implementation. I'd recommend to concentrate the efforts on electrical design. You can use 'ind' and 'cap' components from the analogLib and only specify an electrical values (uH, pF, etc.) .
Use ideal components everywhere, and when a circuit works replace them with the real ones.

varun patial wrote on Mar 21^st, 2012, 10:47pm:

i tried putting capacitance before the output port and that proved to be effective in decreasing my power .

what power do u mean?

Back to top

IP Logged

RFICDUDE

Community Fellow

Offline

Posts: 323

Re: need help
Reply #19 - Mar 22^nd, 2012, 5:23pm

I echo Vladislav's suggested, it is better to focus on the fundamentals of your design and then deal with implementation issues.

To answer your question about 1 inductor versus 2 in series, it is better from an area and loss perspective to use one physical inductor versus two in series to achieve a target inductance value. This is because the total inductance of the spiral inductor structure takes advantage of the mutual inductance between turns as part of the total inductance. When you break the inductor into two series inductors you loose some of the benefit of the mutual inductance because the two inductor are physically separated thereby reducing some of the mutual coupling between the turns in the separate spirals.

For the same inductance and similar Q, the area of a single spiral inductor will be less than two series spiral inductors.

Back to top

IP Logged

varun patial

Junior Member

Offline

Posts: 18

Re: need help
Reply #20 - Mar 24^th, 2012, 5:29am

Thanks a lot Vladislav D and RFICDUDE,
i made use of pi network to tune my amplifier to 2.14GHz which was earlier tuned to 1.5GHz and i designed pi matching network by calculating the impedance graphically before C0(pls refer to schematic) it come out to be 100+j248 and matching this to 50 ohms but i think i m lacking somewhere in my approach. pls suggest that my approach is rite or wrong?

Back to top

IP Logged

RFICDUDE Community Fellow Offline Posts: 323	Re: need help Reply #21 - Mar 24^th, 2012, 11:43am I am a little confused, 100+j248 ohms implies a series inductance of 18.36 nH at 2.15GHz. Your first schematic (the only one with a C0) shows 1nH inductors in series with the gate and source (each), so I am not clear on why the input inductance appears to be so high. Was the impedance 100-j248 at 2.15GHz?
Back to top	IP Logged

varun patial

Junior Member

Offline

Posts: 18

Re: need help
Reply #22 - Mar 25^th, 2012, 12:40am

good morning everyone,
RFICDUDE i will answer to your question tommorrow
I am in big confusion
Vladislav D suggested to use ideal components from analoglib but as i have studied that at high frequencies passive components behaves differently as compare to ideal ones so if i use ideal components their behavior will remain same at high frequencies too.....so why not to use real components?
is those parameters e.g. diameter, no. of turns etc are important only while designing layout ?

Back to top

IP Logged

RFICDUDE

Community Fellow

Offline

Posts: 323

Re: need help
Reply #23 - Mar 25^th, 2012, 1:13pm

Yes, it is true that passive components you design/use are far from ideal, so it does make some sense to account for the differences early in the design.

But, when you are trying to design the circuit from first principles there are too many variables to balance if you are trying to account for all the non ideal parameters.

Right now you are having difficulties with the fundamental problem of matching the circuit and achieving a target or acceptable gain. It would be a validation of your design if you first calculated and simulated the performance with ideal components for the match (it is not going to perform any better than this with real components). As a second step, you would evaluate the impact of using real components (how much does the gain decrease from the ideal case).

Back to top

IP Logged

varun patial Junior Member Offline Posts: 18	Re: need help Reply #24 - Mar 26^th, 2012, 2:36am Thanx a lot @RFICDUDE, as you were asking for the inductance of 18 nH at the input, I found that the current was lagging voltage. So I calculated Vp-p and from there I calculated time difference between both peak, and calculated mod zin .I am attaching the waveform i got
Back to top	varun.png IP Logged

RFICDUDE

Community Fellow

Offline

Posts: 323

Re: need help
Reply #25 - Mar 26^th, 2012, 4:20am

Estimating impedance from the time domain waveform is not the most reliable way to measure impedance.

I suggest using AC simulation to measure input impedance. Driving the input with an AC source you can measure the complex impedance as
z(f)=v(f)/i(f)
then break this down into real and imaginary components to determine what the input looks like at specific frequencies.

The other thing I noticed is that the input signal levels in your simulation are very large. Large enough to cause your amplifier to saturate. This might be part of your gain problem if you are also trying to measure gain with the same signal levels applied.

AC (or s-parameter) simulation will let you look at impedances and gain without overdriving the devices. Usually a designer will verify the linear design with AC (or s-parameter) analysis to make sure gain/matching are correct before moving on to transient or steady-state simulations to measure linearity and gain compression characteristics.

Back to top

IP Logged

varun patial

Junior Member

Offline

Posts: 18

Re: need help
Reply #26 - Mar 29^th, 2012, 1:39am

with warm regards to all,(design using ideal LNA)
1) as per �your point RFICDUCE regarding signal level i was taking it as
-60dBm because as i am designing LNA for WCDMA that has reception range of 2.11GHz to 2.17GHz by that BW of 60MHz.Noise floor was coming out to be
Noise floor (when no electronics noise added)= minimum dectable signal=kTB =-174dBm/Hz + 10log(60MHz)= -96dBm, for some window i was taking it as -60dBm, but still how much below or above can i take this value pls suggest
2) as per your suggestion RFICDUDE i calculated the input impedance by ac analysis but it doesnt give the satisfactory result it when calculated from the calculator comes out to be complex(27.838,72) and this value doesnt fit to design.i also tried s parameter analysis (Z11) it also gave same result i m attachig graphs suggest wether my approach is rite or wrong.
firstly sparameter results and then ac analysis result

Back to top

Screenshot-10.png

« Last Edit: Mar 29^th, 2012, 3:02am by varun patial »

IP Logged

varun patial Junior Member Offline Posts: 18	Re: need help Reply #27 - Mar 29^th, 2012, 1:41am for v(f)/I(f) analysis
Back to top	Screenshot-8.png « Last Edit: Mar 29^th, 2012, 3:03am by varun patial » IP Logged

RFICDUDE

Community Fellow

Offline

Posts: 323

Re: need help
Reply #28 - Mar 29^th, 2012, 4:32am

-60dBm is plenty small, so I am surprised that a -60dBm input signal is creating such large voltage and currents in the input circuit.

It looks like the S parameter and AC analysis results are in agreement (as best that I can tell). It is a good ideal to use the same frequency sweep range when comparing different analysis (AC and S-parameter) because it is difficult to visually look at two different ranges especially when one is linear and the other on a log scale.

At this point I need to ask which schematic are you simulating, and what components are included in the input circuit.
I had been assuming that you are using the original schematic you posted, but that you had removed the input pi network and now all measurements are directly into C0 in series with L2. But I am not sure that is the case because you show an AC current into C1.
So, please post your current simulation schematic to clarify exactly what we are looking at.

Are L1 and L2 fixed values of 1nH in your design (bond wire parasitic), or can you change them as part of your design?

Back to top

IP Logged

varun patial

Junior Member

Offline

Posts: 18

Re: need help
Reply #29 - Mar 31^st, 2012, 6:36am

hello everyone,
hello RFICDUDE, sorry i forget to mention that with your suggestion i replaced the passive components (real) with the ideal ones (analoglib). I will attach the schematic shortly.
But before that i m confused , although it is stupid to ask this question but i didnt think over it earlier.
Its regarding the value of dc blocking capacitor.I was taking it earlier ar 10pF. But after doing some survey i found mixture of answer and now I am not able to find adequate value for dc blocking capacitor both at input and output. pls suggest how its value is choosen
1) I read it that it should be between 0 to 5 percent of input impedance but why so and if its true then for 50 ohms impedance at input impedance 5 percent of it gives 2.5 ohms of Xc so that give value of C (29pF) �at working frequency(2.14GHz). but isnt it large value regarding to area constraint.
2) some relates its value from SFR of capacitor but i am not getting exact answer regarding value.

Back to top

IP Logged