Hello everyone! I am designing a CDR for a 5Gbps SERDES and I cannot figure out how to model deterministic jitter for my testbenches. From literature I've seen that the Dual Dirac model is applied. But if my jitter model applies jitter in the Dual Dirac fashion on each data-UI, the CDR cannot lock. So, should I let jitter take all values between the Dual Dirac edges? I mean, isn't this more "realistic"?

During design spec I had to make a jitter budget. This defines the worst case eye closure in the CDR inputs. Eye closure is due to both random and deterministic jitter.

Now, I have to model random and deterministic jitter for simulations. I use Verilog-A and model random jitter as a normal distribution. For deterministic jitter I use a uniform distribution from which I randomly select the peak values(i.e. Dj_max or -Dj_max). Both jitter values are added per UI in the CDR data input thus closing the data eye.

Problem is that by adding +/-Dj in each UI, the CDR loop cannot track the input signal. That is why I wonder if I should use all intermediate values between [-Dj_max, Dj_max] and not just the peak ones.
I hope it's clear now

CDR system's jitter includes random jitter and deterministic jitter; yet, when we talk about this, we are thinking about the recovered clock or data, which are outputs of the CDR.

For the input of CDR, I cannot see any necessity to put the "deterministic jitter" (which is not a right way to define DJ, I just use your terms).  I think we just need to put random data, or PRBS data as usually the input of a CDR circuit, with some Gaussian distributed noise as loose-electron mentioned.

Correct me if I am not right.