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MOS aspect retio less than 1 (Read 13007 times)
Frank Wiedmann
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Re: MOS aspect retio less than 1
Reply #15 - Apr 11th, 2012, 1:39pm
 
The circuit might not behave in a linear way during the transition, so loop gain theory (which assumes a linear circuit) might not be applicable during this time. This could be an explanation for an overshoot that is higher than predicted by the value of the phase margin.

A phase margin of 60 degrees should be adequate in most cases, 76 degrees are required to have no overshoot of the step response in a second-order system, see for example http://powerelectronics.com/power_systems/simulation_modeling/Transient-response....
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RobG
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Re: MOS aspect retio less than 1
Reply #16 - Apr 11th, 2012, 1:50pm
 
In addition to what Frank said, look at the effect of capacitance on the tail of the diff pair (which can be severely underestimated if you tie the bulk to the source).
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RobG
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Re: MOS aspect retio less than 1
Reply #17 - Apr 11th, 2012, 2:14pm
 
Wow, I just saw your ramping 1.2 in 50 nS. Your problem is probably coming from coupling capacitance. E.g. a 5 fF capacitance will produce a 100 nA current spike.
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mixed_signal
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Re: MOS aspect retio less than 1
Reply #18 - Apr 11th, 2012, 9:35pm
 
Thank you all for the suggestions!
I have the following doubts:

1. I have 2u/20u transistors (length=20u) to layout for current mirror in IBM 130nm tech. Shall I lay a single transistor of length 20u for that? Laying 2 nos. of 1u/20u makes it excess long and will not be of any matching help. OR
Can i tie 10 nos. of 2u length transistors in series with all gates shorted to get equivalent transistor of length 20u as shown in Bakers book?

2. For real implementation, how much gain margin shall we choose for opamp? Is phase margin of 60 not sufficient ?
In my case i increased the gain margin to 10dB from 3 dB and I have the following transient response. Is the spike  acceptable?


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mixed_signal
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Re: MOS aspect retio less than 1
Reply #19 - Apr 19th, 2012, 7:13pm
 
Hi,

Pls help Smiley
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