seanpai
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Hi guys, I am doing an opamp behavior model for my LDO. And when I want to limit my output, there is a error in my simulation. It looks like a discontinuity problem. I don't know how to resolve this problem, so can anyone give me some suggestions? My code is showed below. // VerilogA for lib_cpai_ct369_oa, beh_ldo_hcap_4ct, veriloga
`include "discipline.h" `include "constants.h"
`define PI 3.14159265358979323846264338327950288419716939937511 `define clip(x,L,H) min(H,max(L,x+(H+L)/2))
//-------------------- // opamp // // - operational amplifier // // vin_p,vin_n: differential input voltage [V,A] // vout: output voltage [V,A] // vref: reference voltage [V,A] // vspply_p: positive supply voltage [V,A] // vspply_n: negative supply voltage [V,A] // // INSTANCE parameters // gain = gain [] // freq_unitygain = unity gain frequency [Hz] // rin = input resistance [Ohms] // vin_offset = input offset voltage referred to negative [V] // ibias = input current [A] // iin_max = maximum current [A] // slew_rate = slew rate [A/F] // rout = output resistance [Ohms] // vsoft = soft output limiting value [V] // // MODEL parameters // {none} //
module beh_ldo_opamp_v2(vin_n,vin_p,vdd33,vss33,vout,i50u,pd); input vin_n, vin_p; inout vout, vdd33, vss33, i50u, pd; electrical vout, vin_n, vin_p, vdd33, vss33, i50u, pd; parameter real gain = 810; parameter real freq_unitygain = 557e6; parameter real vin_offset = 0.0; parameter real iin_max = 25e-6; parameter real slew_rate = 17e6; parameter real r2=26K from (0:inf); parameter real ratio=1; parameter real gm_nom= 182.2e-6; parameter real rout=80;
//parameter real gm_out= 155e-6; //parameter real vov_p= 149.3e-3; //152e-3 //parameter real vov_n= 335e-3; //156e-3
parameter real vsoft=0.27; //0.67 branch(vdd33,i50u) res; real c1; real r1; real vmax_in; real vin_val; //electrical cout;
analog function real ftanh; // define a tanh function for output smoothing input x,L,H; real x,L,H,dv; begin dv=(H-L) / 2; ftanh = L+ dv*(1+ tanh(x/dv)); end endfunction
analog begin
@ ( initial_step or initial_step("dc") ) begin //c1 = iin_max/(slew_rate); c1 = gm_nom/ (2 * `PI * freq_unitygain); //gm_nom = 2 * `PI * freq_unitygain * c1; r1 = gain/gm_nom; vmax_in = iin_max/gm_nom; end vin_val = V(vin_n,vin_p) + vin_offset; //pd if (V(pd, vss33) >= 0.5*V(vdd33,vss33)) //see as logic conditonal equation begin I(vdd33, i50u) <+ 0; I(vdd33, vin_n) <+ ratio*I(res); end else begin //i50u current flow V(res) <+ I(res) * r2; //equal to V(vdd33,i50u) <+ I(vdd33,i50u) *r2; I(vdd33, vin_n) <+ ratio*I(res);
// Vout range if ( V(vout,vss33) > (V(vdd33,vss33) - vsoft) ) I(vout, vss33) <+ ftanh((V(vdd33,vss33) - vsoft), vsoft, V(vdd33,vss33)-vsoft )/r1; else if ( V(vout, vss33) < (V(vss33) + vsoft) ) I(vout, vss33) <+ ftanh((V(vdd33,vss33) - vsoft), vsoft, V(vdd33,vss33)-vsoft )/r1; else // GM stage with slewing I(vout, vss33) <+ ftanh( gm_nom*vin_val, -iin_max, iin_max ); end // Dominant Pole. I(vout, vss33) <+ ddt(c1*V(vout, vss33)); I(vout, vss33) <+ V(vout, vss33)/r1; end endmodule Thanks for any reply.
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