Hello there,

I wrote a Verilog AMS Modle for a simple analog LPF:

//Verilog-AMS HDL for "test", "filter2" "verilogams"

`include "constants.vams"
`include "disciplines.vams"

module filter2 ( in, out);
input in;
output out;
electrical in,out;

parameter real tau1= 0.66 from (0:inf);
parameter real tau2= 0.074 from (0:inf);
real Kn;  


// passive filter lead lag

analog begin

Kn=tau2/(tau1+tau2);

V(out)<+Kn*laplace_nd(V(in), {1/tau2,1},{1/(tau1+tau2),1 });

$bound_step(1n);

end

endmodule

When I looked closer at the step response of the filter I saw that there is a abrupt jump in the output signal at the time where the step is applied to the input. That is a bit strange since the output should be continious. Does anyone know what's going wrong here? I am using AMS  solver in ADE XL.

Thanks for your help.

Hi,

but how can i avoid this. I mean it is  a simple LPF , there is not much that I can change, is there?

Regards