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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › help for veriloga sample hold circuit convergence problem.
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help for veriloga sample hold circuit convergence problem. (Read 1948 times)
didibabawu
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help for veriloga sample hold circuit convergence problem.
Apr 30th, 2012, 12:37am  
Hi guys,

I meet a problem of convergence when I use veriloga to model the SH circuit.
I first use veriloga to build the model of capacitor, ideal switch and ideal opamp, but when I do the simulation with spectre, It tell me no convergence, how can I do with this problem?

thx!!
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