Hi,

I'm designing my first voltage-mode  DAC (8 bit). I'm using 0.13 um CMOS technology.
The output voltage of this DAC will be used to set the input reference voltage of a latched comparator working at 100 MHz.
For precision, the DAC needs to have a maximum settling time of 10 ns and +/- 0.5 LSB for DNL and INL and a sampling frequency of at least 5 MHz. Also, I'm looking for low power (< 100 uW) and less than 300 um x 300 um of space.
Load capacitor and resistance are determined by the input mosfet of the comparator. Simulations results gives CL = Cin_mosfet = 2fF and RL_max=2 *10^13.
It seems that the current-steering topology is the best for this, since its a high-speed application. Although, will I be able to achieve low power with this topology ?
Any modification I could do to a standard current-steering topology to lower the power and settling time ?

Thanks for your advice!