library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--------------Data Type------------------------

Package my_data_type1 is

Type p is Array(natural range <>) OF std_logic_vector (m-1 downto 0);
Type C1 is Array(natural range <>) OF std_logic_vector (m-1 downto 0);
Type C2 is Array(natural range <>) OF std_logic_vector (m-1 downto 0);

end my_data_type1;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_data_type1.all;

----------------State Machine--------------------

ENTITY TEMP_COMP1 IS

GENERIC(      n: integer := 10 ; m: integer := 10);
port (      clk,data_ready : in std_logic;
T : in std_logic_vector (m-1 downto 0);
  Z1 : out C1 (0 downto (m-1)**2 )
  Z2 : out C2 (0 downto (m-1)**2 ));

  end temp_comp1;

architecture rtl of temp_comp is

signal P : std_logic_vector(n-1 downto 0);
signal mul_in1 : std_logic_vector ((m-1)**2 downto 0);
signal mul_in2 : std_logic_vector ((m-1)**2 downto 0);
signal mul_out : std_logic_vector ((m-1)**2 downto 0);
signal A1 : std_logic_vector ((m-1)**2 downto 0);
signal A2 : std_logic_vector ((m-1)**2 downto 0);
signal data_ready : std_logic;
signal count : std_logic_vector(n-1 downto 0);

type state is (power , coeff1 , coeff2);
signal CS,NS : state;


begin

process(data_raedy,clk)  
    begin
        if data_ready = '1' then
    CS <= power;
 elsif (rising_edge(clk)) then
            CS <= NS;
    END IF;
end process;

-------------------States----------------------

process(power,P,mul_in1,mul_in2,mul_out,NS,count,Z1,Z2)
begin
    case state is
        when power  =>
     mul_in1 <= T ;
     mul_in2 <= p(count);
   
if count /= n
then  
  count <= count+1;
  p(count+1) <= mul_out;
end if;

NS <= coeff1;

when coeff1 =>
   mul_in1 <= T;
   mul_in2 <= Z1(count);
         
   if count /= n
   then count <= count+1;
   A1 <= mul_out;
end if;

NS <= coeff2;

when coeff2 =>
    mul_in1 <= T;
    mul_in2 <= Z2(count);
   
    if count /= n
 >:(    then count <= count+1;
    A2 <= mul_out;
end if;
   
                     
end case;
end process;

end rtl;