Yutao Liu
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Posts: 76
Guangzhou, China
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Hello reja, The results show as follow, Input frequency = 5000MHz, CML buffer output swing is 364mV for schematic simulation, and 178mV for post-layout simulation. Input frequency = 4050MHz, CML buffer output swing is 590mV for schematic simulation, and 309mV for post-layout simulation.
According to the results above, I agree with that the parasitic capacitor reduces the BW of the buffer. So, increasing bias current and reducing load resistor is the way to enlarge the output swing, isn't it? It seems power consuming. If the input frequency covers a wide frequency range, the buffer waste power when working on lower frequency. Is there any better approach?
By the way, I used to think that limited BW cause incomplete switching in differential pair. What is the difference between them?
Thanks for your help. Yutao
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