Hello everyone,
 I am designing a CML buffer, whose input frequency is up to 5GHz, and its output load is modeled by a 300fF capacitor.  It is driven by a LC-tank VCO.
   In the schematic simulation, the output swing is above 400mV. However,  the output swing is only 240mV in the post-layout simulation. I ran DC simulation and found that there was about 170fF parasitic capacitor on the input line and 60fF on the output line. I suspect that only a little parasitic capacitor can decrease the output swing so much.
  Does the parasitic capacitor cause significant difference? Or something else? Could you give me some advice?

Thanks,
Yutao

Hello reja,
The results show as follow,
Input frequency = 5000MHz, CML buffer output swing is 364mV for schematic simulation, and 178mV for post-layout simulation.
Input frequency = 4050MHz, CML buffer output swing is 590mV for schematic simulation, and 309mV for post-layout simulation.

  According to the results above, I agree with that the parasitic capacitor reduces the BW of the buffer. So, increasing bias current and reducing load resistor is the way to enlarge the output swing, isn't it? It seems power consuming. If the input frequency covers a wide frequency range, the buffer waste power when working on lower frequency. Is there any better approach?

By the way, I used to think that limited BW cause incomplete switching in differential pair. What is the difference between them?

Thanks  for your help.
Yutao